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[50.57.142.19]) by mx.google.com with ESMTPS id o2si985136qag.29.2014.04.08.08.14.47 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 08 Apr 2014 08:14:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xen.org designates 50.57.142.19 as permitted sender) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WXXii-0005PN-AM; Tue, 08 Apr 2014 15:13:52 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WXXif-0005KZ-8s for xen-devel@lists.xensource.com; Tue, 08 Apr 2014 15:13:49 +0000 Received: from [85.158.137.68:16911] by server-8.bemta-3.messagelabs.com id D7/77-21547-C2214435; Tue, 08 Apr 2014 15:13:48 +0000 X-Env-Sender: Stefano.Stabellini@citrix.com X-Msg-Ref: server-12.tower-31.messagelabs.com!1396970026!4261180!1 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n X-StarScan-Received: X-StarScan-Version: 6.11.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 10528 invoked from network); 8 Apr 2014 15:13:47 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-12.tower-31.messagelabs.com with RC4-SHA encrypted SMTP; 8 Apr 2014 15:13:47 -0000 X-IronPort-AV: E=Sophos;i="4.97,818,1389744000"; d="scan'208";a="117915016" Received: from accessns.citrite.net (HELO FTLPEX01CL03.citrite.net) ([10.9.154.239]) by FTLPIPO02.CITRIX.COM with ESMTP; 08 Apr 2014 15:12:52 +0000 Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.80) with Microsoft SMTP Server id 14.2.342.4; Tue, 8 Apr 2014 11:12:52 -0400 Received: from kaball.uk.xensource.com ([10.80.2.59]) by ukmail1.uk.xensource.com with esmtp (Exim 4.69) (envelope-from ) id 1WXXhk-0005Ms-0i; Tue, 08 Apr 2014 16:12:52 +0100 From: Stefano Stabellini To: Date: Tue, 8 Apr 2014 16:12:45 +0100 Message-ID: <1396969969-18973-8-git-send-email-stefano.stabellini@eu.citrix.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-DLP: MIA1 Cc: julien.grall@citrix.com, Ian.Campbell@citrix.com, stefano.stabellini@eu.citrix.com Subject: [Xen-devel] [PATCH v7 08/12] xen/arm: rename GIC_IRQ_GUEST_PENDING to GIC_IRQ_GUEST_QUEUED X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: stefano.stabellini@eu.citrix.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.173 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: Rename GIC_IRQ_GUEST_PENDING to GIC_IRQ_GUEST_QUEUED and clarify its meaning in xen/include/asm-arm/domain.h. Signed-off-by: Stefano Stabellini --- xen/arch/arm/gic.c | 4 ++-- xen/arch/arm/vgic.c | 4 ++-- xen/include/asm-arm/domain.h | 11 ++++++----- 3 files changed, 10 insertions(+), 9 deletions(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 869c077..bed6e9c 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -642,7 +642,7 @@ static inline void gic_set_lr(int lr, struct pending_irq *p, GICH[GICH_LR + lr] = lr_reg; set_bit(GIC_IRQ_GUEST_VISIBLE, &p->status); - clear_bit(GIC_IRQ_GUEST_PENDING, &p->status); + clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status); p->lr = lr; } @@ -723,7 +723,7 @@ static void gic_update_one_lr(struct vcpu *v, int i) p->desc->status &= ~IRQ_INPROGRESS; clear_bit(GIC_IRQ_GUEST_VISIBLE, &p->status); p->lr = GIC_INVALID_LR; - if ( test_bit(GIC_IRQ_GUEST_PENDING, &p->status) && + if ( test_bit(GIC_IRQ_GUEST_QUEUED, &p->status) && test_bit(GIC_IRQ_GUEST_ENABLED, &p->status)) { inflight = 1; diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index 3913cf5..6a89a1e 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -700,7 +700,7 @@ void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq) { if ( (irq != current->domain->arch.evtchn_irq) || (!test_bit(GIC_IRQ_GUEST_VISIBLE, &n->status)) ) - set_bit(GIC_IRQ_GUEST_PENDING, &n->status); + set_bit(GIC_IRQ_GUEST_QUEUED, &n->status); goto out; } @@ -714,7 +714,7 @@ void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq) priority = byte_read(rank->ipriority[REG_RANK_INDEX(8, idx)], 0, byte); n->irq = irq; - set_bit(GIC_IRQ_GUEST_PENDING, &n->status); + set_bit(GIC_IRQ_GUEST_QUEUED, &n->status); n->priority = priority; /* the irq is enabled */ diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index 2d94d59..f96dc12 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -27,7 +27,8 @@ struct pending_irq * whether an irq added to an LR register is PENDING or ACTIVE, the * following states are just an approximation. * - * GIC_IRQ_GUEST_PENDING: the irq is asserted + * GIC_IRQ_GUEST_QUEUED: the irq is asserted and queued for + * injection into the guests LRs. * * GIC_IRQ_GUEST_VISIBLE: the irq has been added to an LR register, * therefore the guest is aware of it. From the guest point of view @@ -35,12 +36,12 @@ struct pending_irq * or active (after acking the irq). * * In order for the state machine to be fully accurate, for level - * interrupts, we should keep the GIC_IRQ_GUEST_PENDING state until + * interrupts, we should keep the GIC_IRQ_GUEST_QUEUED state until * the guest deactivates the irq. However because we are not sure - * when that happens, we simply remove the GIC_IRQ_GUEST_PENDING + * when that happens, we simply remove the GIC_IRQ_GUEST_QUEUED * state when we add the irq to an LR register. We add it back when * we receive another interrupt notification. - * Therefore it is possible to set GIC_IRQ_GUEST_PENDING while the + * Therefore it is possible to set GIC_IRQ_GUEST_QUEUED while the * irq is GIC_IRQ_GUEST_VISIBLE. We could also change the state of * the guest irq in the LR register from active to active and * pending, but for simplicity we simply inject a second irq after @@ -54,7 +55,7 @@ struct pending_irq * level (GICD_ICENABLER/GICD_ISENABLER). * */ -#define GIC_IRQ_GUEST_PENDING 0 +#define GIC_IRQ_GUEST_QUEUED 0 #define GIC_IRQ_GUEST_VISIBLE 1 #define GIC_IRQ_GUEST_ENABLED 2 unsigned long status;