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[50.57.142.19]) by mx.google.com with ESMTPS id p8si7532091qag.260.2014.05.13.04.31.27 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 13 May 2014 04:31:27 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WkAu4-000803-Vr; Tue, 13 May 2014 11:29:49 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WkAu2-0007xE-DK for xen-devel@lists.xen.org; Tue, 13 May 2014 11:29:46 +0000 Received: from [193.109.254.147:22356] by server-10.bemta-14.messagelabs.com id E5/FB-04546-92202735; Tue, 13 May 2014 11:29:45 +0000 X-Env-Sender: Ian.Campbell@citrix.com X-Msg-Ref: server-11.tower-27.messagelabs.com!1399980583!1175944!1 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n X-StarScan-Received: X-StarScan-Version: 6.11.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 21119 invoked from network); 13 May 2014 11:29:44 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-11.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 13 May 2014 11:29:44 -0000 X-IronPort-AV: E=Sophos; i="4.97,1043,1389744000"; d="scan'208"; a="129769999" Received: from accessns.citrite.net (HELO FTLPEX01CL03.citrite.net) ([10.9.154.239]) by FTLPIPO02.CITRIX.COM with ESMTP; 13 May 2014 11:29:43 +0000 Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.80) with Microsoft SMTP Server id 14.3.181.6; Tue, 13 May 2014 07:29:43 -0400 Received: from marilith-n13-p0.uk.xensource.com ([10.80.229.115] helo=localhost.localdomain) by ukmail1.uk.xensource.com with smtp (Exim 4.69) (envelope-from ) id 1WkAtx-0004Xq-QN; Tue, 13 May 2014 12:29:42 +0100 Received: by localhost.localdomain (sSMTP sendmail emulation); Tue, 13 May 2014 12:29:41 +0100 From: Ian Campbell To: Date: Tue, 13 May 2014 12:29:32 +0100 Message-ID: <1399980574-12515-8-git-send-email-ian.campbell@citrix.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1399980488.21867.19.camel@kazak.uk.xensource.com> References: <1399980488.21867.19.camel@kazak.uk.xensource.com> MIME-Version: 1.0 X-DLP: MIA2 Cc: ian.jackson@eu.citrix.com, julien.grall@linaro.org, tim@xen.org, Ian Campbell , stefano.stabellini@eu.citrix.com Subject: [Xen-devel] [PATCH v4 8/9] tools: arm: support up to (almost) 1TB of guest RAM X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ian.campbell@citrix.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.181 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: This creates a second bank of RAM starting at 8GB and potentially extending to the 1TB boundary, which is the limit imposed by our current use of a 3 level p2m with 2 pages at level 0 (2^40 bits). I've deliberately left a gap between the two banks just to exercise those code paths. The second bank is 1016GB in size which plus the 3GB below 4GB is 1019GB maximum guest RAM. At the point where the fact that this is slightly less than a full TB starts to become an issue for people then we can switch to a 4 level p2m, which would be needed to support guests larger than 1TB anyhow. Tested on 32-bit with 1, 4 and 6GB guests. Anything more than ~3GB requires an LPAE enabled kernel, or a 64-bit guest. Signed-off-by: Ian Campbell --- v4: Significantly reworked (simplified) due to changes in earlier patches. Removed existing Acks. v3: remove inadvertent whitespace change --- tools/libxc/xc_dom_arm.c | 4 ++-- tools/libxl/libxl_arm.c | 4 ++-- xen/include/public/arch-arm.h | 9 ++++++--- 3 files changed, 10 insertions(+), 7 deletions(-) diff --git a/tools/libxc/xc_dom_arm.c b/tools/libxc/xc_dom_arm.c index c83965d..549caa1 100644 --- a/tools/libxc/xc_dom_arm.c +++ b/tools/libxc/xc_dom_arm.c @@ -287,10 +287,10 @@ int arch_setup_meminit(struct xc_dom_image *dom) uint64_t ramsize = (uint64_t)dom->total_pages << XC_PAGE_SHIFT; const uint64_t bankbase[GUEST_RAM_BANKS] = { - GUEST_RAM0_BASE + GUEST_RAM0_BASE, GUEST_RAM1_BASE }; const uint64_t bankmax[GUEST_RAM_BANKS] = { - GUEST_RAM0_SIZE + GUEST_RAM0_SIZE, GUEST_RAM1_SIZE }; /* Convenient */ diff --git a/tools/libxl/libxl_arm.c b/tools/libxl/libxl_arm.c index 90fca67..058bed3 100644 --- a/tools/libxl/libxl_arm.c +++ b/tools/libxl/libxl_arm.c @@ -261,7 +261,7 @@ static int make_memory_nodes(libxl__gc *gc, void *fdt, int res, i; const char *name; const uint64_t bankbase[GUEST_RAM_BANKS] = { - GUEST_RAM0_BASE + GUEST_RAM0_BASE, GUEST_RAM1_BASE }; for (i = 0; i < GUEST_RAM_BANKS; i++) { @@ -560,7 +560,7 @@ int libxl__arch_domain_finalise_hw_description(libxl__gc *gc, void *fdt = dom->devicetree_blob; int i; const uint64_t bankbase[GUEST_RAM_BANKS] = { - GUEST_RAM0_BASE + GUEST_RAM0_BASE, GUEST_RAM1_BASE }; const struct xc_dom_seg *ramdisk = dom->ramdisk_blob ? diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h index 96c8786..935a1eb 100644 --- a/xen/include/public/arch-arm.h +++ b/xen/include/public/arch-arm.h @@ -375,14 +375,17 @@ typedef uint64_t xen_callback_t; #define GUEST_MAGIC_BASE 0x39000000ULL #define GUEST_MAGIC_SIZE 0x01000000ULL -#define GUEST_RAM_BANKS 1 +#define GUEST_RAM_BANKS 2 -#define GUEST_RAM0_BASE 0x40000000ULL /* 3GB of RAM @ 1GB */ +#define GUEST_RAM0_BASE 0x40000000ULL /* 3GB of low RAM @ 1GB */ #define GUEST_RAM0_SIZE 0xc0000000ULL +#define GUEST_RAM1_BASE 0x0200000000ULL /* 1016GB of RAM @ 8GB */ +#define GUEST_RAM1_SIZE 0xfe00000000ULL + #define GUEST_RAM_BASE GUEST_RAM0_BASE /* Lowest RAM address */ /* Largest amount of actual RAM, not including holes */ -#define GUEST_RAM_MAX (GUEST_RAM0_SIZE) +#define GUEST_RAM_MAX (GUEST_RAM0_SIZE + GUEST_RAM1_SIZE) /* Interrupts */ #define GUEST_TIMER_VIRT_PPI 27