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[50.57.142.19]) by mx.google.com with ESMTPS id tr4si12443062igb.7.2014.07.14.09.41.10 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 14 Jul 2014 09:41:11 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1X6jHb-0007EZ-75; Mon, 14 Jul 2014 16:39:19 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1X6jHZ-0007EA-8O for xen-devel@lists.xen.org; Mon, 14 Jul 2014 16:39:17 +0000 Received: from [193.109.254.147:27409] by server-5.bemta-14.messagelabs.com id A9/DD-05821-4B704C35; Mon, 14 Jul 2014 16:39:16 +0000 X-Env-Sender: Ian.Campbell@citrix.com X-Msg-Ref: server-14.tower-27.messagelabs.com!1405355954!17377181!1 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n X-StarScan-Received: X-StarScan-Version: 6.11.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 22475 invoked from network); 14 Jul 2014 16:39:15 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-14.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 14 Jul 2014 16:39:15 -0000 X-IronPort-AV: E=Sophos;i="5.01,659,1400025600"; d="scan'208";a="152692632" Received: from accessns.citrite.net (HELO FTLPEX01CL03.citrite.net) ([10.9.154.239]) by FTLPIPO02.CITRIX.COM with ESMTP; 14 Jul 2014 16:39:14 +0000 Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.80) with Microsoft SMTP Server id 14.3.181.6; Mon, 14 Jul 2014 12:39:13 -0400 Received: from drall.uk.xensource.com ([10.80.16.71]) by ukmail1.uk.xensource.com with smtp (Exim 4.69) (envelope-from ) id 1X6jHU-0008Rh-Ff; Mon, 14 Jul 2014 17:39:13 +0100 Received: by drall.uk.xensource.com (sSMTP sendmail emulation); Mon, 14 Jul 2014 17:39:12 +0100 From: Ian Campbell To: Date: Mon, 14 Jul 2014 17:39:08 +0100 Message-ID: <1405355950-6461-3-git-send-email-ian.campbell@citrix.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1405355930.31863.5.camel@kazak.uk.xensource.com> References: <1405355930.31863.5.camel@kazak.uk.xensource.com> MIME-Version: 1.0 X-DLP: MIA1 Cc: julien.grall@linaro.org, tim@xen.org, Ian Campbell , stefano.stabellini@eu.citrix.com Subject: [Xen-devel] [PATCH 3/5] xen: arm: Do not use level 0 section mappings in boot page tables. X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ian.campbell@citrix.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.178 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: Level 0 does not support superpage mappings, meaning that systems on where Xen is loaded above 512GB (I'm not aware of any such systems) the 1:1 mapping on the boot page tables is invalid. In order to avoid this issue we need an additional first level page table mapped by the appropriate L0 slot and containing a 1:1 superpage mapping. Signed-off-by: Ian Campbell --- xen/arch/arm/arm64/head.S | 22 +++++++++++++++++++--- xen/arch/arm/mm.c | 3 +++ 2 files changed, 22 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index 3f46f43..023a9b9 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -267,14 +267,30 @@ skip_bss: orr x2, x1, x3 /* + rights for linear PT */ str x2, [x4, #0] /* Map it in slot 0 */ - /* ... map of paddr(start) in boot_pgtable */ + /* ... map of paddr(start) in boot_pgtable+boot_first_id */ lsr x1, x19, #ZEROETH_SHIFT/* Offset of base paddr in boot_pgtable */ cbz x1, 1f /* It's in slot 0, map in boot_first * or boot_second later on */ - lsl x2, x1, #ZEROETH_SHIFT /* Base address for 512GB mapping */ - mov x3, #PT_MEM /* x2 := Section mapping */ + /* Level zero does not support superpage mappings, so we have + * to use an extra first level page in which we create a 1GB mapping. + */ + ldr x2, =boot_first_id + add x2, x2, x20 /* x2 := paddr (boot_first_id) */ + + mov x3, #PT_PT /* x2 := table map of boot_first_id */ + orr x2, x2, x3 /* + rights for linear PT */ + lsl x1, x1, #3 /* x1 := Slot offset */ + str x2, [x4, x1] + + ldr x4, =boot_first_id /* Next level into boot_first_id */ + add x4, x4, x20 /* x4 := paddr(boot_first_id) */ + + lsr x1, x19, #FIRST_SHIFT /* x1 := Offset of base paddr in boot_first_id */ + lsl x2, x1, #FIRST_SHIFT /* x2 := Base address for 1GB mapping */ + mov x3, #PT_MEM /* x2 := Section map */ orr x2, x2, x3 + lsl x1, x1, #3 /* x1 := Slot offset */ str x2, [x4, x1] /* Mapping of paddr(start)*/ diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index fdc7c98..0a243b0 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -68,6 +68,7 @@ struct domain *dom_xen, *dom_io, *dom_cow; lpae_t boot_pgtable[LPAE_ENTRIES] __attribute__((__aligned__(4096))); #ifdef CONFIG_ARM_64 lpae_t boot_first[LPAE_ENTRIES] __attribute__((__aligned__(4096))); +lpae_t boot_first_id[LPAE_ENTRIES] __attribute__((__aligned__(4096))); #endif lpae_t boot_second[LPAE_ENTRIES] __attribute__((__aligned__(4096))); lpae_t boot_third[LPAE_ENTRIES] __attribute__((__aligned__(4096))); @@ -491,6 +492,8 @@ void __init setup_pagetables(unsigned long boot_phys_offset, paddr_t xen_paddr) #ifdef CONFIG_ARM_64 memset(boot_first, 0x0, PAGE_SIZE); clean_and_invalidate_xen_dcache(boot_first); + memset(boot_first_id, 0x0, PAGE_SIZE); + clean_and_invalidate_xen_dcache(boot_first_id); #endif memset(boot_second, 0x0, PAGE_SIZE); clean_and_invalidate_xen_dcache(boot_second);