From patchwork Fri Sep 5 10:09:53 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: wangyijing X-Patchwork-Id: 36802 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qg0-f69.google.com (mail-qg0-f69.google.com [209.85.192.69]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 0D3D0202E4 for ; Fri, 5 Sep 2014 09:54:34 +0000 (UTC) Received: by mail-qg0-f69.google.com with SMTP id q108sf6311428qgd.8 for ; Fri, 05 Sep 2014 02:54:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:date:message-id:in-reply-to :references:mime-version:cc:subject:precedence:list-id :list-unsubscribe:list-post:list-help:list-subscribe:sender :errors-to:x-original-sender:x-original-authentication-results :mailing-list:list-archive:content-type:content-transfer-encoding; bh=FiRAB+Ug0iKR7yKPW4/spaD0mdgEoOpQ3VxKSY6JGJk=; b=VgEdB7YvmXztxhY2x08W/g/2iGegETwoCJPzlXggxcJzyi4aStEgZKcCKTtq/FxFRr RvXpNmL78pWVB42Q9QJY8+7VsAEu7PKypEvwttDuq+wQQ1vCiqjizLTQ+Ww/VHPFLWtd UvogJE5Vef+xPRkAMaz1/G/b+HENzDFf6Fpdr4jYMN0BFATaVd1QV4bpTIJ+hTG3FjHx dT8ds9kxpmO8pyYOVBFUtg11p/oFCD6g2fp2EL9EOz4p325kKID6y8dNu4onBexV70Ar j54Zz84na3J1eH9Ym6PqHia2cft2jbLoRMaOJQyYD5T37846uPmXihZeqSJwPOfyI6M2 dCsA== X-Gm-Message-State: ALoCoQll7eXq2o3/058DI4FPWd/tJryTnuQywfYOjR1B89t++xrwTah50doe1CNziQUjzQu4Wscw X-Received: by 10.52.170.204 with SMTP id ao12mr6279625vdc.2.1409910873892; Fri, 05 Sep 2014 02:54:33 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.46.100 with SMTP id j91ls622849qga.44.gmail; Fri, 05 Sep 2014 02:54:33 -0700 (PDT) X-Received: by 10.52.94.108 with SMTP id db12mr7817411vdb.8.1409910873820; Fri, 05 Sep 2014 02:54:33 -0700 (PDT) Received: from mail-vc0-f179.google.com (mail-vc0-f179.google.com [209.85.220.179]) by mx.google.com with ESMTPS id dx5si906866vdb.10.2014.09.05.02.54.33 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 05 Sep 2014 02:54:33 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.179 as permitted sender) client-ip=209.85.220.179; Received: by mail-vc0-f179.google.com with SMTP id hy4so11859108vcb.24 for ; Fri, 05 Sep 2014 02:54:33 -0700 (PDT) X-Received: by 10.221.6.201 with SMTP id ol9mr9416884vcb.2.1409910873721; Fri, 05 Sep 2014 02:54:33 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.221.45.67 with SMTP id uj3csp57212vcb; Fri, 5 Sep 2014 02:54:33 -0700 (PDT) X-Received: by 10.220.105.201 with SMTP id u9mr9322189vco.11.1409910873259; Fri, 05 Sep 2014 02:54:33 -0700 (PDT) Received: from lists.xen.org (lists.xen.org. [50.57.142.19]) by mx.google.com with ESMTPS id hv8si911539vdb.6.2014.09.05.02.54.32 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 05 Sep 2014 02:54:33 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XPqCv-0007A2-6g; Fri, 05 Sep 2014 09:53:29 +0000 Received: from mail6.bemta4.messagelabs.com ([85.158.143.247]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XPqCt-00077x-WC for xen-devel@lists.xenproject.org; Fri, 05 Sep 2014 09:53:28 +0000 Received: from [85.158.143.35:34644] by server-3.bemta-4.messagelabs.com id 49/38-06192-71889045; Fri, 05 Sep 2014 09:53:27 +0000 X-Env-Sender: wangyijing@huawei.com X-Msg-Ref: server-14.tower-21.messagelabs.com!1409910803!11897721!1 X-Originating-IP: [119.145.14.64] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTE5LjE0NS4xNC42NCA9PiA4MDE5MQ==\n X-StarScan-Received: X-StarScan-Version: 6.11.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 6175 invoked from network); 5 Sep 2014 09:53:26 -0000 Received: from szxga01-in.huawei.com (HELO szxga01-in.huawei.com) (119.145.14.64) by server-14.tower-21.messagelabs.com with RC4-SHA encrypted SMTP; 5 Sep 2014 09:53:26 -0000 Received: from 172.24.2.119 (EHLO szxeml419-hub.china.huawei.com) ([172.24.2.119]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CBG93443; Fri, 05 Sep 2014 17:45:49 +0800 (CST) Received: from localhost.localdomain (10.175.100.166) by szxeml419-hub.china.huawei.com (10.82.67.158) with Microsoft SMTP Server id 14.3.158.1; Fri, 5 Sep 2014 17:45:39 +0800 From: Yijing Wang To: Bjorn Helgaas Date: Fri, 5 Sep 2014 18:09:53 +0800 Message-ID: <1409911806-10519-9-git-send-email-wangyijing@huawei.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1409911806-10519-1-git-send-email-wangyijing@huawei.com> References: <1409911806-10519-1-git-send-email-wangyijing@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.100.166] X-CFilter-Loop: Reflected Cc: linux-mips@linux-mips.org, linux-ia64@vger.kernel.org, linux-pci@vger.kernel.org, Bharat.Bhushan@freescale.com, Yijing Wang , sparclinux@vger.kernel.org, linux-arch@vger.kernel.org, linux-s390@vger.kernel.org, Russell King , Joerg Roedel , x86@kernel.org, Sebastian Ott , Benjamin Herrenschmidt , xen-devel@lists.xenproject.org, arnab.basu@freescale.com, Arnd Bergmann , Chris Metcalf , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, Xinwei Hu , Tony Luck , Ralf Baechle , iommu@lists.linux-foundation.org, Wuyun , linuxppc-dev@lists.ozlabs.org, "David S. Miller" Subject: [Xen-devel] [PATCH v1 08/21] x86/xen/MSI: Use MSI chip framework to configure MSI/MSI-X irq X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: wangyijing@huawei.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.179 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: Use MSI chip framework instead of arch MSI functions to configure MSI/MSI-X irq. So we can manage MSI/MSI-X irq in a unified framework. Signed-off-by: Yijing Wang CC: Konrad Rzeszutek Wilk Acked-by: David Vrabel --- arch/x86/pci/xen.c | 46 ++++++++++++++++++++++++++++++---------------- 1 files changed, 30 insertions(+), 16 deletions(-) diff --git a/arch/x86/pci/xen.c b/arch/x86/pci/xen.c index 84c2fce..e669ee4 100644 --- a/arch/x86/pci/xen.c +++ b/arch/x86/pci/xen.c @@ -376,6 +376,11 @@ static void xen_initdom_restore_msi_irqs(struct pci_dev *dev) } #endif +static void xen_teardown_msi_irq(unsigned int irq) +{ + xen_destroy_irq(irq); +} + static void xen_teardown_msi_irqs(struct pci_dev *dev) { struct msi_desc *msidesc; @@ -385,19 +390,26 @@ static void xen_teardown_msi_irqs(struct pci_dev *dev) xen_pci_frontend_disable_msix(dev); else xen_pci_frontend_disable_msi(dev); - - /* Free the IRQ's and the msidesc using the generic code. */ - default_teardown_msi_irqs(dev); -} - -static void xen_teardown_msi_irq(unsigned int irq) -{ - xen_destroy_irq(irq); + + list_for_each_entry(msidesc, &dev->msi_list, list) { + int i, nvec; + if (msidesc->irq == 0) + continue; + if (msidesc->nvec_used) + nvec = msidesc->nvec_used; + else + nvec = 1 << msidesc->msi_attrib.multiple; + for (i = 0; i < nvec; i++) + xen_teardown_msi_irq(msidesc->irq + i); + } } void xen_nop_msi_mask(struct irq_data *data) { } + +struct msi_chip xen_msi_chip; + #endif int __init pci_xen_init(void) @@ -418,9 +430,9 @@ int __init pci_xen_init(void) #endif #ifdef CONFIG_PCI_MSI - x86_msi.setup_msi_irqs = xen_setup_msi_irqs; - x86_msi.teardown_msi_irq = xen_teardown_msi_irq; - x86_msi.teardown_msi_irqs = xen_teardown_msi_irqs; + xen_msi_chip.setup_irqs = xen_setup_msi_irqs; + xen_msi_chip.teardown_irqs = xen_teardown_msi_irqs; + x86_msi_chip = &xen_msi_chip; msi_chip.irq_mask = xen_nop_msi_mask; msi_chip.irq_unmask = xen_nop_msi_mask; #endif @@ -441,8 +453,9 @@ int __init pci_xen_hvm_init(void) #endif #ifdef CONFIG_PCI_MSI - x86_msi.setup_msi_irqs = xen_hvm_setup_msi_irqs; - x86_msi.teardown_msi_irq = xen_teardown_msi_irq; + xen_msi_chip.setup_irqs = xen_hvm_setup_msi_irqs; + xen_msi_chip.teardown_irq = xen_teardown_msi_irq; + x86_msi_chip = &xen_msi_chip; #endif return 0; } @@ -499,9 +512,10 @@ int __init pci_xen_initial_domain(void) int irq; #ifdef CONFIG_PCI_MSI - x86_msi.setup_msi_irqs = xen_initdom_setup_msi_irqs; - x86_msi.teardown_msi_irq = xen_teardown_msi_irq; - x86_msi.restore_msi_irqs = xen_initdom_restore_msi_irqs; + xen_msi_chip.setup_irqs = xen_initdom_setup_msi_irqs; + xen_msi_chip.teardown_irq = xen_teardown_msi_irq; + xen_msi_chip.restore_irqs = xen_initdom_restore_msi_irqs; + x86_msi_chip = &xen_msi_chip; msi_chip.irq_mask = xen_nop_msi_mask; msi_chip.irq_unmask = xen_nop_msi_mask; #endif