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([185.25.64.249]) by mx.google.com with ESMTPSA id fw6sm14830368wib.1.2015.01.19.08.29.49 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 19 Jan 2015 08:29:49 -0800 (PST) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Mon, 19 Jan 2015 16:29:09 +0000 Message-Id: <1421684957-29884-3-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1421684957-29884-1-git-send-email-julien.grall@linaro.org> References: <1421684957-29884-1-git-send-email-julien.grall@linaro.org> Cc: stefano.stabellini@citrix.com, Julien Grall , tim@xen.org, ian.campbell@citrix.com Subject: [Xen-devel] [PATCH 02/10] xen/arm: vgic-v3: Correctly set GICD_TYPER.CPUNumber X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.170 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: On GICv3, the value (CPUNumber + 1) indicates the number of processor that may be used as interrupts targets when ARE bit is zero. The maximum is 8 processors. Signed-off-by: Julien Grall --- The current code of the vGIC doesn't support ARE = 0. Nonetheless, the patch is a candidate for backporing to Xen 4.5 to have a consistent vGIC driver. --- xen/arch/arm/vgic-v3.c | 7 ++++++- xen/include/asm-arm/gic.h | 1 + 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 8420c09..406ea93 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -673,11 +673,16 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, mmio_info_t *info) case GICD_TYPER: { unsigned int irqs = v->domain->arch.vgic.nr_lines + 32; + /* + * Number of processors that may be used as interrupt targets when ARE + * bit is zero. The maximum is 8. + */ + unsigned int ncpus = min_t(unsigned int, v->domain->max_vcpus, 8); unsigned int order; if ( dabt.size != DABT_WORD ) goto bad_width; /* No secure world support for guests. */ - *r = (((v->domain->max_vcpus << 5) & GICD_TYPE_CPUS ) | + *r = ((ncpus - 1) << GICD_TYPE_CPUS_SHIFT | ((v->domain->arch.vgic.nr_lines / 32) & GICD_TYPE_LINES)); /* diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 187dc46..0396a8e 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -93,6 +93,7 @@ #define GICD_CTL_ENABLE 0x1 #define GICD_TYPE_LINES 0x01f +#define GICD_TYPE_CPUS_SHIFT 5 #define GICD_TYPE_CPUS 0x0e0 #define GICD_TYPE_SEC 0x400