From patchwork Mon Mar 2 15:42:43 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 45291 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-la0-f71.google.com (mail-la0-f71.google.com [209.85.215.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id A16102149C for ; Mon, 2 Mar 2015 15:46:20 +0000 (UTC) Received: by labge10 with SMTP id ge10sf24629209lab.3 for ; Mon, 02 Mar 2015 07:46:19 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:date:message-id:cc:subject :precedence:list-id:list-unsubscribe:list-post:list-help :list-subscribe:mime-version:content-type:content-transfer-encoding :sender:errors-to:x-original-sender :x-original-authentication-results:mailing-list:list-archive; bh=5xzDTtCn0AY8vbtkQlu5Tn0CLhmCGm+ORGkpQg4VBXQ=; b=RCxx/0JjZHp+nvhkeXffaXijglfhyLjHUzWvQNW7m4tpDBexVH5pOZWaXtkONvZdSo j6kJgn23/yTwJRSw0CeXbOnLI/318oGOfm9PrBkFIZpQ/txbqXzgmmZDYm14AC3RvoED kdlwNIEqAECj5VGa9EGmj1Nauc8+n1+DIbGe5cV7kVzPg0r000Fwg4x6Io62EAybY1QU qoEdYFuyiia8sp4jZSPMiiGWcWdxHQxP98ZTPGHYIJXL5prPpS2AEH/X9eDeQtsFEbjw MqFa6tFNbPkhJTIS6OA+E/lx74JvoTrNeiOtgDZIplRwv0uSHEx/yCjuOj9HWk8rdnqy C6eg== X-Gm-Message-State: ALoCoQkLXMrVVYTrE2LBYJAUGtcU4IfxQTG9+MDDTdDhTzKQtKHeS1RA6XG8HKxm0T+9YLyMm2zn X-Received: by 10.180.91.76 with SMTP id cc12mr2310988wib.7.1425311179503; Mon, 02 Mar 2015 07:46:19 -0800 (PST) X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.115.140 with SMTP id jo12ls468434lab.19.gmail; Mon, 02 Mar 2015 07:46:19 -0800 (PST) X-Received: by 10.152.22.229 with SMTP id h5mr1071185laf.21.1425311179335; Mon, 02 Mar 2015 07:46:19 -0800 (PST) Received: from mail-la0-f47.google.com (mail-la0-f47.google.com. [209.85.215.47]) by mx.google.com with ESMTPS id t9si9107781lal.77.2015.03.02.07.46.19 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 02 Mar 2015 07:46:19 -0800 (PST) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.47 as permitted sender) client-ip=209.85.215.47; Received: by labgq15 with SMTP id gq15so31277095lab.3 for ; Mon, 02 Mar 2015 07:46:19 -0800 (PST) X-Received: by 10.152.87.3 with SMTP id t3mr24923658laz.19.1425311179205; Mon, 02 Mar 2015 07:46:19 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.35.133 with SMTP id h5csp5604672lbj; Mon, 2 Mar 2015 07:46:18 -0800 (PST) X-Received: by 10.55.17.154 with SMTP id 26mr6220641qkr.66.1425311177856; Mon, 02 Mar 2015 07:46:17 -0800 (PST) Received: from lists.xen.org (lists.xen.org. [50.57.142.19]) by mx.google.com with ESMTPS id 35si948445qkp.32.2015.03.02.07.46.14 (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 02 Mar 2015 07:46:17 -0800 (PST) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1YSSV2-0003jT-4e; Mon, 02 Mar 2015 15:43:16 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1YSSV1-0003jJ-9R for xen-devel@lists.xenproject.org; Mon, 02 Mar 2015 15:43:15 +0000 Received: from [85.158.137.68] by server-7.bemta-3.messagelabs.com id 2A/C9-03163-21584F45; Mon, 02 Mar 2015 15:43:14 +0000 X-Env-Sender: julien.grall@linaro.org X-Msg-Ref: server-11.tower-31.messagelabs.com!1425310993!12321608!1 X-Originating-IP: [74.125.82.53] X-SpamReason: No, hits=0.5 required=7.0 tests=BODY_RANDOM_LONG X-StarScan-Received: X-StarScan-Version: 6.13.4; banners=-,-,- X-VirusChecked: Checked Received: (qmail 10548 invoked from network); 2 Mar 2015 15:43:13 -0000 Received: from mail-wg0-f53.google.com (HELO mail-wg0-f53.google.com) (74.125.82.53) by server-11.tower-31.messagelabs.com with RC4-SHA encrypted SMTP; 2 Mar 2015 15:43:13 -0000 Received: by wghl18 with SMTP id l18so34220335wgh.7 for ; Mon, 02 Mar 2015 07:43:13 -0800 (PST) X-Received: by 10.181.8.103 with SMTP id dj7mr36781853wid.75.1425310993203; Mon, 02 Mar 2015 07:43:13 -0800 (PST) Received: from chilopoda.uk.xensource.com. ([185.25.64.249]) by mx.google.com with ESMTPSA id lx10sm19725603wjb.17.2015.03.02.07.43.11 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 02 Mar 2015 07:43:12 -0800 (PST) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Mon, 2 Mar 2015 15:42:43 +0000 Message-Id: <1425310963-20948-1-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 2.1.4 Cc: stefano.stabellini@citrix.com, Julien Grall , tim@xen.org, ian.campbell@citrix.com Subject: [Xen-devel] [PATCH v5] xen/iommu: smmu: Advertise when the SMMU support coherent table walk X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.47 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: When SMMU doesn't support coherent table walk, Xen may need to clean updated PT (see commit 4c5f4cb "xen/arm: p2m: Clean cache PT when the IOMMU doesn't support coherent walk"). If one SMMU of the platform doesn't support coherent table walk, the feature is disabled for the whole platform. This is because device is assigned to a domain after the page table are populated. This could impact performance on domain which doesn't use device passthrough. But, as the spec strongly recommends the support of this feature for mainstream platform, I expect server will always have SMMUs supporting coherent table walk. If not, we may need to enable this feature per-domain. Signed-off-by: Julien Grall --- I've just noticed that the support on the previous driver (i.e in Xen 4.5) may incorrectly expose this feature when all the SMMUs is not supporting coherent table walk. I'm not sure, if I should send a patch for it. Also I didn't squash this patch into "xen/iommu: smmu: Add Xen specific code to be able to use the driver" to help for review and to catch possible error in this patch. Changes in v5: - Create a separate function to find the SMMU - Typoes Changes in v4: - Browse the list to retrieve the last SMMU added. - Take the spinlock Changes in v3: - Patch added --- xen/drivers/passthrough/arm/smmu.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/arm/smmu.c index 7675767..a7a7da9 100644 --- a/xen/drivers/passthrough/arm/smmu.c +++ b/xen/drivers/passthrough/arm/smmu.c @@ -2531,6 +2531,13 @@ MODULE_LICENSE("GPL v2"); /* Xen only supports stage-2 translation, so force the value to 2. */ static int force_stage = 2; +/* + * Platform features. It indicates the list of features supported by all + * SMMUs. + * Actually we only care about coherent table walk. + */ +static u32 platform_features = ARM_SMMU_FEAT_COHERENT_WALK; + static void arm_smmu_iotlb_flush_all(struct domain *d) { struct arm_smmu_xen_domain *smmu_domain = domain_hvm_iommu(d)->arch.priv; @@ -2668,6 +2675,10 @@ static int arm_smmu_iommu_domain_init(struct domain *d) domain_hvm_iommu(d)->arch.priv = xen_domain; + /* Coherent walk can be enabled only when all SMMUs support it. */ + if (platform_features & ARM_SMMU_FEAT_COHERENT_WALK) + iommu_set_feature(d, IOMMU_FEAT_COHERENT_WALK); + return 0; } @@ -2738,10 +2749,28 @@ static const struct iommu_ops arm_smmu_iommu_ops = { .unmap_page = arm_smmu_unmap_page, }; +static __init const struct arm_smmu_device *find_smmu(const struct device *dev) +{ + struct arm_smmu_device *smmu; + bool found = false; + + spin_lock(&arm_smmu_devices_lock); + list_for_each_entry(smmu, &arm_smmu_devices, list) { + if (smmu->dev == dev) { + found = true; + break; + } + } + spin_unlock(&arm_smmu_devices_lock); + + return (found) ? smmu : NULL; +} + static __init int arm_smmu_dt_init(struct dt_device_node *dev, const void *data) { int rc; + const struct arm_smmu_device *smmu; /* * Even if the device can't be initialized, we don't want to @@ -2755,6 +2784,12 @@ static __init int arm_smmu_dt_init(struct dt_device_node *dev, iommu_set_ops(&arm_smmu_iommu_ops); + /* Find the last SMMU added and retrieve its features. */ + smmu = find_smmu(dt_to_dev(dev)); + BUG_ON(smmu == NULL); + + platform_features &= smmu->features; + return 0; }