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[50.57.142.19]) by mx.google.com with ESMTPS id s9si18675960qct.40.2015.04.28.07.49.28 (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 28 Apr 2015 07:49:28 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Yn6oJ-00019D-QE; Tue, 28 Apr 2015 14:48:31 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Yn6oH-00015Z-C2 for xen-devel@lists.xenproject.org; Tue, 28 Apr 2015 14:48:29 +0000 Received: from [85.158.139.211] by server-2.bemta-5.messagelabs.com id EC/A2-12190-CBD9F355; Tue, 28 Apr 2015 14:48:28 +0000 X-Env-Sender: julien.grall@citrix.com X-Msg-Ref: server-12.tower-206.messagelabs.com!1430232502!11277468!4 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n, received_headers: No Received headers X-StarScan-Received: X-StarScan-Version: 6.13.14; banners=-,-,- X-VirusChecked: Checked Received: (qmail 6611 invoked from network); 28 Apr 2015 14:48:27 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-12.tower-206.messagelabs.com with RC4-SHA encrypted SMTP; 28 Apr 2015 14:48:27 -0000 X-IronPort-AV: E=Sophos;i="5.11,664,1422921600"; d="scan'208";a="259453194" From: Julien Grall To: Date: Tue, 28 Apr 2015 15:32:40 +0100 Message-ID: <1430231563-25648-17-git-send-email-julien.grall@citrix.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1430231563-25648-1-git-send-email-julien.grall@citrix.com> References: <1430231563-25648-1-git-send-email-julien.grall@citrix.com> MIME-Version: 1.0 X-DLP: MIA1 Cc: Wei Liu , ian.campbell@citrix.com, tim@xen.org, Julien Grall , Ian Jackson , stefano.stabellini@citrix.com Subject: [Xen-devel] [PATCH v6 16/19] tools/libxl: arm: Use an higher value for the GIC phandle X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: patch@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.170 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: From: Julien Grall The partial device tree may contains phandle. The Device Tree Compiler tends to allocate the phandle from 1. Reserve the ID 65000 for the GIC phandle. I think we can safely assume that the partial device tree will never contain a such ID. Signed-off-by: Julien Grall Acked-by: Ian Campbell Cc: Ian Jackson Cc: Wei Liu --- To allocate dynamically the phandle, we would need to fill in post-hoc (like we do with e.g the initramfs location) the #interrupt-parent in "/". That would also require some refactoring in the code to pass the phandle every time. Defer this solution to a follow-up in order as having 65000 would be very unlikely. Changes in v6: - Add a note in the doc about the reserved phandle Changes in v5: - Add Ian C.'s Ack. Changes in v3: - Patch added --- docs/man/xl.cfg.pod.5 | 3 +++ tools/libxl/libxl_arm.c | 9 +++++---- tools/libxl/libxl_types.idl | 2 ++ 3 files changed, 10 insertions(+), 4 deletions(-) diff --git a/docs/man/xl.cfg.pod.5 b/docs/man/xl.cfg.pod.5 index ad95a9a..1a9bd52 100644 --- a/docs/man/xl.cfg.pod.5 +++ b/docs/man/xl.cfg.pod.5 @@ -470,6 +470,9 @@ the user to defined aliases which can be used by the guest kernel. Given the complexity of verifying the validity of a device tree, this option should only be used with trusted device tree. +Note that the partial device tree should avoid to use the phandle 65000 +which is reserved by the toolstack. + =back =head2 Devices diff --git a/tools/libxl/libxl_arm.c b/tools/libxl/libxl_arm.c index a3fb3b4..a2633cb 100644 --- a/tools/libxl/libxl_arm.c +++ b/tools/libxl/libxl_arm.c @@ -80,10 +80,11 @@ static struct arch_info { {"xen-3.0-aarch64", "arm,armv8-timer", "arm,armv8" }, }; -enum { - PHANDLE_NONE = 0, - PHANDLE_GIC, -}; +/* + * The device tree compiler (DTC) is allocating the phandle from 1 to + * onwards. Reserve a high value for the GIC phandle. + */ +#define PHANDLE_GIC (65000) typedef uint32_t be32; typedef be32 gic_interrupt[3]; diff --git a/tools/libxl/libxl_types.idl b/tools/libxl/libxl_types.idl index 09a2414..5f9e6ae 100644 --- a/tools/libxl/libxl_types.idl +++ b/tools/libxl/libxl_types.idl @@ -415,6 +415,8 @@ libxl_domain_build_info = Struct("domain_build_info",[ # Given the complexity of verifying the validity of a device tree, # libxl doesn't do any security check on it. It's the responsibility # of the caller to provide only trusted device tree. + # Note that the partial device tree should avoid to use the phandle + # 65000 which is reserved by the toolstack. ("device_tree", string), ("u", KeyedUnion(None, libxl_domain_type, "type", [("hvm", Struct(None, [("firmware", string),