From patchwork Thu Dec 15 06:13:14 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupinder Thakur X-Patchwork-Id: 88112 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp619436qgi; Wed, 14 Dec 2016 22:15:29 -0800 (PST) X-Received: by 10.36.2.14 with SMTP id 14mr1023740itu.113.1481782529514; Wed, 14 Dec 2016 22:15:29 -0800 (PST) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id f63si7859843ith.72.2016.12.14.22.15.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 14 Dec 2016 22:15:29 -0800 (PST) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cHPIG-00064Z-HE; Thu, 15 Dec 2016 06:13:28 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cHPIF-00064T-FM for xen-devel@lists.xenproject.org; Thu, 15 Dec 2016 06:13:27 +0000 Received: from [85.158.139.211] by server-7.bemta-5.messagelabs.com id 1D/E2-19310-68432585; Thu, 15 Dec 2016 06:13:26 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrCIsWRWlGSWpSXmKPExsXiVRusp9tqEhR h0PCIy+L7lslMDowehz9cYQlgjGLNzEvKr0hgzTjX1MZW8Fq7YsW1/0wNjI1KXYycHEICMxgl WveLdjFycbAIzGOWOLh1CgtIQkKgn1Xi1J0oCDtG4tOWqUwQdoXEz8ttbBDNWhJHT81mBWkWE mhhkviz8hZzFyMHB5uAicSsDgmQGhEBJYl7qyaD9TILhEr8e9bGDmILC7hJrHm+lhXEZhFQlb jReZIZxOYV8Ja41fKIGWKXnMTNc51gNqeAj8TH+Q1MEHu9JY6ueMc4gVFgASPDKkaN4tSistQ iXSNTvaSizPSMktzEzBxdQwNTvdzU4uLE9NScxKRiveT83E2MwLCqZ2Bg3MG4q93vEKMkB5OS KO8ho6AIIb6k/JTKjMTijPii0pzU4kOMMhwcShK8ycZAOcGi1PTUirTMHGCAw6QlOHiURHiZg EEuxFtckJhbnJkOkTrFaMwx7dnip0wcOzrXPGUSYsnLz0uVEuflA5kkAFKaUZoHNwgWeZcYZa WEeRkZGBiEeApSi3IzS1DlXzGKczAqCfMqgkzhycwrgdv3CugUJqBTRJf4g5xSkoiQkmpgNDp e+L6D/1D+zvM/e93sDiksePbl7Ls27k9XH33O4gjOtzipNMHQ6ptw91M1p9lNZ2pZreM8PZn1 shn8v1uxy3VO4L7+dDIPt5eyf1XA57R7P/sPtWgeTC2dYX9HZVrWmti7t7P2bT/4frbwnITus j5ljnNcGdwychNE//0+fH/l03jex75hSizFGYmGWsxFxYkArfZSrLcCAAA= X-Env-Sender: bhupinder.thakur@linaro.org X-Msg-Ref: server-5.tower-206.messagelabs.com!1481782404!73887094!1 X-Originating-IP: [74.125.83.46] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.1.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 18391 invoked from network); 15 Dec 2016 06:13:25 -0000 Received: from mail-pg0-f46.google.com (HELO mail-pg0-f46.google.com) (74.125.83.46) by server-5.tower-206.messagelabs.com with AES128-GCM-SHA256 encrypted SMTP; 15 Dec 2016 06:13:25 -0000 Received: by mail-pg0-f46.google.com with SMTP id x23so16544654pgx.1 for ; Wed, 14 Dec 2016 22:13:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=y1tfA4zpmPlgRj/BuDd7Q0ec3+3nA1HkADjlSNzc4tE=; b=hCXYxxNXAOFY+uzV+p2cwPdCe/+130N11GimeHw82R1XxRd9vcgQT3bYxWV3eob3MC JdYjGmMP0a1S9SCOjuEdaDrLGjsNMZZ6UCa9Z7darfKI3IPJFnNtKnR+roHQy6q6+Ity XmmUH7/uyCHcypsTOnJSOs+0GYVLB1yMwxx5U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=y1tfA4zpmPlgRj/BuDd7Q0ec3+3nA1HkADjlSNzc4tE=; b=gmGrcvh0rvQIlzEV3PWMrOQ7I5kZFUxwQRH29EpeGHcwNh8XCITErwISeAiGrQsWEn e8c9eHGJMXROMN8aQSy7l7M60MTcodBf4txrMj/VBDa/lHmxCmXBfgX3ZVoNS0q7qBLs okF53r+DBmctag8Ec3eyfjLE2pglXs15LnMo/5DVdhJqC9YyPytLovG0ce76rqUbObw1 ey+Bw4PsM5BcybwpKfeJ01a7kPk5+3nzHgiOUw153We6g1ZHIP2ZnYOWwqgb3JsJqw2T ySLlnuuTNCfozRQqw8t1LDn/boLAAHtcAh772mSFXuHAUFhiZuBKpNs+22RIraNCdZ4J 1Qwg== X-Gm-Message-State: AKaTC0191vlg8pnc2zPXAVVl95syTWbsldpCTCRjqfXnQvHdSupNt/oiP8RvQKR939Yf1CB2 X-Received: by 10.99.44.84 with SMTP id s81mr1200392pgs.153.1481782403198; Wed, 14 Dec 2016 22:13:23 -0800 (PST) Received: from blr-ubuntu-linaro.wlan.qualcomm.com ([202.46.23.54]) by smtp.gmail.com with ESMTPSA id 64sm1097985pfu.17.2016.12.14.22.13.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Dec 2016 22:13:22 -0800 (PST) From: Bhupinder Thakur To: xen-devel@lists.xenproject.org Date: Thu, 15 Dec 2016 11:43:14 +0530 Message-Id: <1481782394-14285-2-git-send-email-bhupinder.thakur@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1481782394-14285-1-git-send-email-bhupinder.thakur@linaro.org> References: <1481782394-14285-1-git-send-email-bhupinder.thakur@linaro.org> Cc: Julien Grall , Stefano Stabellini Subject: [Xen-devel] [XEN VMID PATCH 2/2 v4] xen/arm: Add support for 16 bit VMIDs X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" VMID space is increased to 16-bits from 8-bits in ARMv8 8.1 revision. This allows more than 256 VMs to be supported by Xen. This change adds support for 16-bit VMIDs in Xen based on whether the architecture supports it. Signed-off-by: Bhupinder Thakur --- xen/arch/arm/p2m.c | 45 +++++++++++++++++++++++++++++++++++------ xen/include/asm-arm/p2m.h | 2 +- xen/include/asm-arm/processor.h | 18 ++++++++++++++++- 3 files changed, 57 insertions(+), 8 deletions(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 2327509..b166122 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -14,15 +15,23 @@ #include #include +#define MAX_VMID_8_BIT (1UL << 8) +#define MAX_VMID_16_BIT (1UL << 16) + +#define INVALID_VMID 0 /* VMID 0 is reserved */ + #ifdef CONFIG_ARM_64 static unsigned int __read_mostly p2m_root_order; static unsigned int __read_mostly p2m_root_level; #define P2M_ROOT_ORDER p2m_root_order #define P2M_ROOT_LEVEL p2m_root_level +static unsigned int __read_mostly max_vmid = MAX_VMID_8_BIT; +#define MAX_VMID max_vmid #else /* First level P2M is alway 2 consecutive pages */ #define P2M_ROOT_LEVEL 1 #define P2M_ROOT_ORDER 1 +#define MAX_VMID MAX_VMID_8_BIT #endif #define P2M_ROOT_PAGES (1<root = page; - p2m->vttbr = page_to_maddr(p2m->root) | ((uint64_t)p2m->vmid & 0xff) << 48; + p2m->vttbr = page_to_maddr(p2m->root) | ((uint64_t)p2m->vmid << 48); /* * Make sure that all TLBs corresponding to the new VMID are flushed @@ -1230,19 +1239,27 @@ static int p2m_alloc_table(struct domain *d) return 0; } -#define MAX_VMID 256 -#define INVALID_VMID 0 /* VMID 0 is reserved */ static spinlock_t vmid_alloc_lock = SPIN_LOCK_UNLOCKED; /* - * VTTBR_EL2 VMID field is 8 bits. Using a bitmap here limits us to - * 256 concurrent domains. + * VTTBR_EL2 VMID field is 8 or 16 bits. Aarch64 supports 16-bit VMID. + * Using a bitmap here limits us to 256 or 65536 (for Aarch64) concurrent + * domains. The bitmap space will be allocated dynamically based on + * whether 8 or 16 bit VMIDs are supported. */ -static DECLARE_BITMAP(vmid_mask, MAX_VMID); +static unsigned long *vmid_mask; static void p2m_vmid_allocator_init(void) { + /* + * allocate space for vmid_mask based on MAX_VMID + */ + vmid_mask = xzalloc_array(unsigned long, BITS_TO_LONGS(MAX_VMID)); + + if ( !vmid_mask ) + panic("Could not allocate VMID bitmap space"); + set_bit(INVALID_VMID, vmid_mask); } @@ -1632,20 +1649,36 @@ void __init setup_virt_paging(void) unsigned int cpu; unsigned int pa_range = 0x10; /* Larger than any possible value */ + bool vmid_8_bit = false; for_each_online_cpu ( cpu ) { const struct cpuinfo_arm *info = &cpu_data[cpu]; if ( info->mm64.pa_range < pa_range ) pa_range = info->mm64.pa_range; + + /* set a flag if the current cpu does not suppot 16 bit VMIDs */ + if ( info->mm64.vmid_bits != MM64_VMID_16_BITS_SUPPORT ) + vmid_8_bit = true; } + /* + * if the flag is not set then it means all CPUs support 16-bit + * VMIDs. + */ + if ( !vmid_8_bit ) + max_vmid = MAX_VMID_16_BIT; + /* pa_range is 4 bits, but the defined encodings are only 3 bits */ if ( pa_range&0x8 || !pa_range_info[pa_range].pabits ) panic("Unknown encoding of ID_AA64MMFR0_EL1.PARange %x\n", pa_range); val |= VTCR_PS(pa_range); val |= VTCR_TG0_4K; + + /* set the VS bit only if 16 bit VMID is supported */ + if ( MAX_VMID == MAX_VMID_16_BIT ) + val |= VTCR_VS; val |= VTCR_SL0(pa_range_info[pa_range].sl0); val |= VTCR_T0SZ(pa_range_info[pa_range].t0sz); diff --git a/xen/include/asm-arm/p2m.h b/xen/include/asm-arm/p2m.h index 0987be2..9de55fc 100644 --- a/xen/include/asm-arm/p2m.h +++ b/xen/include/asm-arm/p2m.h @@ -30,7 +30,7 @@ struct p2m_domain { struct page_info *root; /* Current VMID in use */ - uint8_t vmid; + uint16_t vmid; /* Current Translation Table Base Register for the p2m */ uint64_t vttbr; diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index 15bf890..48ce59b 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -215,6 +215,8 @@ #define VTCR_PS(x) ((x)<<16) +#define VTCR_VS (_AC(0x1,UL)<<19) + #endif #define VTCR_RES1 (_AC(1,UL)<<31) @@ -269,6 +271,11 @@ /* FSR long format */ #define FSRL_STATUS_DEBUG (_AC(0x22,UL)<<0) +#ifdef CONFIG_ARM_64 +#define MM64_VMID_8_BITS_SUPPORT 0x0 +#define MM64_VMID_16_BITS_SUPPORT 0x2 +#endif + #ifndef __ASSEMBLY__ struct cpuinfo_arm { @@ -337,7 +344,16 @@ struct cpuinfo_arm { unsigned long tgranule_64K:4; unsigned long tgranule_4K:4; unsigned long __res0:32; - }; + + unsigned long hafdbs:4; + unsigned long vmid_bits:4; + unsigned long vh:4; + unsigned long hpds:4; + unsigned long lo:4; + unsigned long pan:4; + unsigned long __res1:8; + unsigned long __res2:32; + }; } mm64; struct {