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[192.237.175.120]) by mx.google.com with ESMTPS id e64si5357849ith.193.2017.08.14.07.26.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 14 Aug 2017 07:26:17 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dhGIg-0000vB-O8; Mon, 14 Aug 2017 14:25:02 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dhGIf-0000q5-Ae for xen-devel@lists.xen.org; Mon, 14 Aug 2017 14:25:01 +0000 Received: from [85.158.139.211] by server-11.bemta-5.messagelabs.com id 9B/DA-01729-CB2B1995; Mon, 14 Aug 2017 14:25:00 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrELMWRWlGSWpSXmKPExsVysyfVTXfnpom RBnu38Vgs+biYxYHR4+ju30wBjFGsmXlJ+RUJrBl7bv9nKfgoVHH09ir2BsZnfF2MnBxCApsZ JZqPSHQxcgHZpxkl3tx+wQqSYBPQlLjz+RMTiC0iIC1x7fNlRhCbWSBS4vCHH+wgtrCAh8Tah fvZQGwWAVWJnr1tYL28AlYSc1cfZwGxJQTkJXa1XQSLcwLFO+/uZIFYbClxYvVstgmM3AsYGV YxahSnFpWlFukaWeolFWWmZ5TkJmbm6BoamOrlphYXJ6an5iQmFesl5+duYgT6t56BgXEH4+U tfocYJTmYlER5E3x6I4X4kvJTKjMSizPii0pzUosPMcpwcChJ8N7YODFSSLAoNT21Ii0zBxho MGkJDh4lEYg0b3FBYm5xZjpE6hSjLserCf+/MQmx5OXnpUqJ85aDFAmAFGWU5sGNgAX9JUZZK WFeRgYGBiGegtSi3MwSVPlXjOIcjErCvKIbgKbwZOaVwG16BXQEE9ARfSD38xaXJCKkpBoYbV hWM63YbmZ299ipm7l+6YoqTZ+s2bfy7Mxye7Qg/szb2MoPH/f0SVjc43+xTsvs7M8dnbv81qS 3vX0SqlHXfMlankcnrV/U/ZWOduZDp+INxV6CN49daj5WKpTzY5nz4ipXRXFjTZGDZ3dJmZyc MvfBY0buz6p2aUKCdh3XlXl2X2YMM9qjxFKckWioxVxUnAgA5PB7nHUCAAA= X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-6.tower-206.messagelabs.com!1502720696!104364661!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests=UPPERCASE_25_50 X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 16781 invoked from network); 14 Aug 2017 14:24:57 -0000 Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-6.tower-206.messagelabs.com with SMTP; 14 Aug 2017 14:24:57 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6D0AD1991; Mon, 14 Aug 2017 07:24:56 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8173F3F483; Mon, 14 Aug 2017 07:24:55 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 14 Aug 2017 15:24:10 +0100 Message-Id: <20170814142418.13267-20-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170814142418.13267-1-julien.grall@arm.com> References: <20170814142418.13267-1-julien.grall@arm.com> Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH 19/27] xen/arm: page: Clean-up the definition of MAIRVAL X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" Currently MAIRVAL is defined in term of MAIR0VAL and MAIR1VAL which are both hardcoded value. This makes quite difficult to understand the value written in both registers. Rework the definition by using value of each attribute shifted by their associated index. Signed-off-by: Julien Grall Reviewed-by: Andre Przywara --- xen/include/asm-arm/page.h | 43 +++++++++++++++++++++++++------------------ 1 file changed, 25 insertions(+), 18 deletions(-) diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h index d7a048b64d..86b227c291 100644 --- a/xen/include/asm-arm/page.h +++ b/xen/include/asm-arm/page.h @@ -22,6 +22,21 @@ #define LPAE_SH_INNER 0x3 /* + * Attribute Indexes. + * + * These are valid in the AttrIndx[2:0] field of an LPAE stage 1 page + * table entry. They are indexes into the bytes of the MAIR* + * registers, as defined above. + * + */ +#define MT_UNCACHED 0x0 +#define MT_BUFFERABLE 0x1 +#define MT_WRITETHROUGH 0x2 +#define MT_WRITEBACK 0x3 +#define MT_DEV_SHARED 0x4 +#define MT_WRITEALLOC 0x7 + +/* * LPAE Memory region attributes. Indexed by the AttrIndex bits of a * LPAE entry; the 8-bit fields are packed little-endian into MAIR0 and MAIR1. * @@ -35,26 +50,18 @@ * reserved 110 * MT_WRITEALLOC 111 1111 1111 -- Write-back write-allocate * - * MT_DEV_WC 001 (== BUFFERABLE) */ -#define MAIR0VAL 0xeeaa4400 -#define MAIR1VAL 0xff000004 -#define MAIRVAL (MAIR0VAL|MAIR1VAL<<32) +#define MAIR(attr, mt) (_AC(attr, ULL) << ((mt) * 8)) -/* - * Attribute Indexes. - * - * These are valid in the AttrIndx[2:0] field of an LPAE stage 1 page - * table entry. They are indexes into the bytes of the MAIR* - * registers, as defined above. - * - */ -#define MT_UNCACHED 0x0 -#define MT_BUFFERABLE 0x1 -#define MT_WRITETHROUGH 0x2 -#define MT_WRITEBACK 0x3 -#define MT_DEV_SHARED 0x4 -#define MT_WRITEALLOC 0x7 +#define MAIRVAL (MAIR(0x00, MT_UNCACHED) | \ + MAIR(0x44, MT_BUFFERABLE) | \ + MAIR(0xaa, MT_WRITETHROUGH) | \ + MAIR(0xee, MT_WRITEBACK) | \ + MAIR(0x04, MT_DEV_SHARED) | \ + MAIR(0xff, MT_WRITEALLOC)) + +#define MAIR0VAL (MAIRVAL & 0xffffffff) +#define MAIR1VAL (MAIRVAL >> 32) #define PAGE_HYPERVISOR (MT_WRITEALLOC) #define PAGE_HYPERVISOR_NOCACHE (MT_DEV_SHARED)