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[192.237.175.120]) by mx.google.com with ESMTPS id w69si98220ith.131.2018.01.31.08.55.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 31 Jan 2018 08:55:59 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=N50jYn6N; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1egvdo-00041k-MI; Wed, 31 Jan 2018 16:53:44 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1egvdn-00041b-PQ for xen-devel@lists.xen.org; Wed, 31 Jan 2018 16:53:43 +0000 X-Inumbo-ID: 420d5c23-06a7-11e8-ba59-bc764e045a96 Received: from mail-wr0-x243.google.com (unknown [2a00:1450:400c:c0c::243]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id 420d5c23-06a7-11e8-ba59-bc764e045a96; Wed, 31 Jan 2018 17:53:28 +0100 (CET) Received: by mail-wr0-x243.google.com with SMTP id h9so2738773wre.12 for ; Wed, 31 Jan 2018 08:53:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vlZuztuqXFHwOF9vWd8kU2lGJYgXgGOt/WpDlhU7dPU=; b=N50jYn6NZrTNODs2ceRNyU7hzjUKeUFy6f4ZsQOhFA0IhFsTkG0gO0PpbY15hqdnKm r9yeGQHER9o5mre3no0pea2+W+AjhcSEg700PoLAHbqu0fu2YCgZlO42d6mg2bPLt5nT riyh9JYuWDRoraXApmPsKXshoTPmBEWoBx3uM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vlZuztuqXFHwOF9vWd8kU2lGJYgXgGOt/WpDlhU7dPU=; b=N3CxRrgT8I9omNiqY/9EMSQcfI8Xr9Z0Orh6Je0Op2nHjyxB4no4+Do/xb9PH3OfIz 7DSVqxQmUcKCvdjnS1Hl9kUHjsM2QalSHL2fgbu3yYyGLcIfXp9lftBs0+YR8MWsXTvr zwXmsK5HMmFTq6gWtgCV9SJ+lNMtvQYdasdFJyFL8WOFkODQkX9VfZD7S29QvG21gpDo Z8//gCzJJcGkXNMumfFVcWATWrxr5x2D3GdRyLQv/iHUqB0fxbPZAcECHsD2cxZtFIaO B0m0ZtClOD1L8hFlAUd6N1mvZVKoWbOuUs2Ez84+3+EBHWpxtBMv/wgTBfGUXUjI9oub DAJQ== X-Gm-Message-State: AKwxytd0xAjPDcyJipibXJ34ZnPqv2AcuMtazGPgCQTAa+18y2xunEL/ F1GFx/ff+uAT9OUWwz3PS8BeJnojZd4= X-Received: by 10.223.129.67 with SMTP id 61mr26473152wrm.271.1517417620962; Wed, 31 Jan 2018 08:53:40 -0800 (PST) Received: from e108454-lin.cambridge.arm.com ([2001:41d0:1:6c23::1]) by smtp.gmail.com with ESMTPSA id h194sm223745wma.8.2018.01.31.08.53.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 31 Jan 2018 08:53:40 -0800 (PST) From: Julien Grall X-Google-Original-From: Julien Grall To: xen-devel@lists.xen.org Date: Wed, 31 Jan 2018 16:53:29 +0000 Message-Id: <20180131165334.23175-3-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180131165334.23175-1-julien.grall@arm.com> References: <20180131165334.23175-1-julien.grall@arm.com> Cc: sstabellini@kernel.org, Julien Grall , andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v2 2/7] xen/arm32: Add missing MIDR values for Cortex-A17 and A12 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Julien Grall Cortex-A17 and A12 MIDR will be used in a follow-up patch for hardening the branch predictor. This is part of XSA-254. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- Changes in v2: - Add Stefano's reviewed-by --- xen/include/asm-arm/processor.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index 466da5da86..c0f79d0093 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -44,6 +44,8 @@ #define ARM_CPU_IMP_ARM 0x41 +#define ARM_CPU_PART_CORTEX_A12 0xC0D +#define ARM_CPU_PART_CORTEX_A17 0xC0E #define ARM_CPU_PART_CORTEX_A15 0xC0F #define ARM_CPU_PART_CORTEX_A53 0xD03 #define ARM_CPU_PART_CORTEX_A57 0xD07 @@ -51,6 +53,8 @@ #define ARM_CPU_PART_CORTEX_A73 0xD09 #define ARM_CPU_PART_CORTEX_A75 0xD0A +#define MIDR_CORTEX_A12 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A12) +#define MIDR_CORTEX_A17 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A17) #define MIDR_CORTEX_A15 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A15) #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)