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[192.237.175.120]) by mx.google.com with ESMTPS id 6si1770032iob.240.2018.02.02.06.21.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 02 Feb 2018 06:21:52 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=gMIxAu0c; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ehcBh-00085C-Lh; Fri, 02 Feb 2018 14:19:33 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ehcBf-00084f-RO for xen-devel@lists.xen.org; Fri, 02 Feb 2018 14:19:31 +0000 X-Inumbo-ID: 0ad158b7-0824-11e8-ba59-bc764e045a96 Received: from mail-wm0-x243.google.com (unknown [2a00:1450:400c:c09::243]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id 0ad158b7-0824-11e8-ba59-bc764e045a96; Fri, 02 Feb 2018 15:19:13 +0100 (CET) Received: by mail-wm0-x243.google.com with SMTP id j21-v6so2811056wmh.1 for ; Fri, 02 Feb 2018 06:19:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/bIAb0tmbXs5lKUzW8ga62dax57uVS3tbVmOakqWBLM=; b=gMIxAu0czxdtF85NuNoxUNXdrPTJ9EZu2EwLrabCb6V1IrkOlVVjGbis9zqC4YLZ48 hFw7QjSy/h8fCcWoEyozOHI9qyNfafR8lydqLop7nC7qCXHO/fud/Pl8IaJV7ToCGMAz GH1+mRHdShPts5FVi9ND//zxhgmOqipQ+STRE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/bIAb0tmbXs5lKUzW8ga62dax57uVS3tbVmOakqWBLM=; b=HbI7jwxgW0a9i7A7Y3rWYgMk7nBZBlAx4CzRtsCF1YRwZEKh7ySuep88bLU2ZO0knR tniHr8RBlteYVhhfjCsFVitOH61kJ7awerpY3uk5FIeBNlHErKzBy45lPFhMCy2OjYFM a2ml/QkW55p4E2vGEvOiDa8ZN2dllXM2dHVg82TiqvavhH8/y0+jXCDZUhReifviMoVc QA7Z0f9s/wtcU/eQSLpUYK6HXJ/qR3+8PwIz81FsNjFxZZ1hZ/eN5LoX55bGstzGn8cw /vInucf1p5L4MOkbm88HOyUH3SFvO2cyhJkHMVqDyVtUiPl9O8seMqGn8DiRqzOMQrFU 1yYw== X-Gm-Message-State: AKwxyteHSbEsJYOy5dGdNgiFljxApgkAClPfMfiN2UvXa70xL93Lg6im FJuzI8R0c3mdyDBeReKzVPATUk3B9X8= X-Received: by 10.28.232.82 with SMTP id f79mr2161702wmh.72.1517581169425; Fri, 02 Feb 2018 06:19:29 -0800 (PST) Received: from e108454-lin.cambridge.arm.com ([2001:41d0:1:6c23::1]) by smtp.gmail.com with ESMTPSA id u79sm3057422wma.10.2018.02.02.06.19.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 02 Feb 2018 06:19:28 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 2 Feb 2018 14:19:20 +0000 Message-Id: <20180202141925.19387-3-julien.grall@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180202141925.19387-1-julien.grall@linaro.org> References: <20180202141925.19387-1-julien.grall@linaro.org> Cc: sstabellini@kernel.org, Julien Grall , andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v4 2/7] xen/arm32: Add missing MIDR values for Cortex-A17 and A12 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Cortex-A17 and A12 MIDR will be used in a follow-up patch for hardening the branch predictor. This is part of XSA-254. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- Changes in v2: - Add Stefano's reviewed-by --- xen/include/asm-arm/processor.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index 466da5da86..c0f79d0093 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -44,6 +44,8 @@ #define ARM_CPU_IMP_ARM 0x41 +#define ARM_CPU_PART_CORTEX_A12 0xC0D +#define ARM_CPU_PART_CORTEX_A17 0xC0E #define ARM_CPU_PART_CORTEX_A15 0xC0F #define ARM_CPU_PART_CORTEX_A53 0xD03 #define ARM_CPU_PART_CORTEX_A57 0xD07 @@ -51,6 +53,8 @@ #define ARM_CPU_PART_CORTEX_A73 0xD09 #define ARM_CPU_PART_CORTEX_A75 0xD0A +#define MIDR_CORTEX_A12 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A12) +#define MIDR_CORTEX_A17 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A17) #define MIDR_CORTEX_A15 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A15) #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)