From patchwork Thu Feb 8 19:21:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 127736 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1793969ljc; Thu, 8 Feb 2018 11:24:37 -0800 (PST) X-Google-Smtp-Source: AH8x225aZ18uIS+nifoTYbO2+jzHQv5ajOUiI1VVdOOFYJIrakuAyXfwODnFOW0bxk6Ve3GOlitA X-Received: by 10.107.176.14 with SMTP id z14mr164666ioe.8.1518117877314; Thu, 08 Feb 2018 11:24:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518117877; cv=none; d=google.com; s=arc-20160816; b=QesBiIW4v51SHcZzuXEy3snZM210rMOZxMRuIqELuFPgMZ5aiPukPSVr3lKdRrp25f giKjc4KtZUc8+OnAYFMFGBxH1tR0484DsQpO0Aw0Kjd0F5zOuMB+5jU02BZqa/NlLSGg YOLqXIJk9TmES5LaQwWgWH4ER+6kS42UN4j2Q8zU8+q3UVf3IOKcLnp5Mv7AGCKvhmqx ImllM5mjuZJK5ClNQXKClyrbp0cvuqT7w6bFQ0GgInpEW7/2TJwqQ7nahNgYHe51RJbM b9dmRgpIOJPzO4Tz4h8jOHXOu108tOzQvoT16o0OnmgNnUqebODLK9Qo/+Pb2H5PJNMo NpHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=6dITXwq/9wmioU7fyGAMQEQmD+ctWIVBZBFD54oTagM=; b=kTF2Y3BGyMVFBx9s3BtkfZ0pBNERcnum0tPNuYrSUJyx4VTX2x54Fza1hSvTmuriVv P8c5JpZF7rFtXeQFytiuPvmE9Ze8EjIBwafL4Q0zW8EPgyO3Tce0wJQ2JOZiW7ywXRxF S1Vl6ioH3TK9P8Yc8V5j3K6cvvz1aSyUynDwEV8dtfJ0Jr8ztkDW/cPYfsHORSQjKgH4 BDWMpZpLZ8zvaRG2ELs1L+4CyQ9VhKPTjRf1kl0zEyFSc9+QOxqMLz4C/HqlmSoTsSNw mLRLHcFvPkgpj+9WjNxZFxXXR+9gg/WYn0kq0MJGd/yDLcfM4UhdA4FGks0eHJOl8bMS aYzA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id n74si513108iod.222.2018.02.08.11.24.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Feb 2018 11:24:37 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrmE-0006V3-2A; Thu, 08 Feb 2018 19:22:34 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrmD-0006MR-AN for xen-devel@lists.xen.org; Thu, 08 Feb 2018 19:22:33 +0000 X-Inumbo-ID: 86bd5a50-0d05-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 86bd5a50-0d05-11e8-b9b1-635ca7ef6cff; Thu, 08 Feb 2018 19:23:22 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5436680D; Thu, 8 Feb 2018 11:22:26 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 451473F24D; Thu, 8 Feb 2018 11:22:25 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 8 Feb 2018 19:21:59 +0000 Message-Id: <20180208192203.9556-12-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180208192203.9556-1-julien.grall@arm.com> References: <20180208192203.9556-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v2 11/15] xen/arm64: Add ARM_SMCCC_ARCH_WORKAROUND_1 BP hardening support X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Add the detection and runtime code for ARM_SMCCC_ARCH_WORKAROUND_1. Signed-off-by: Julien Grall --- Changes in v2: - Patch added --- xen/arch/arm/arm64/bpi.S | 12 ++++++++++++ xen/arch/arm/cpuerrata.c | 32 +++++++++++++++++++++++++++++++- xen/include/asm-arm/smccc.h | 1 + 3 files changed, 44 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/arm64/bpi.S b/xen/arch/arm/arm64/bpi.S index 4b7f1dc21f..ef237de7bd 100644 --- a/xen/arch/arm/arm64/bpi.S +++ b/xen/arch/arm/arm64/bpi.S @@ -16,6 +16,8 @@ * along with this program. If not, see . */ +#include + .macro ventry target .rept 31 nop @@ -81,6 +83,16 @@ ENTRY(__psci_hyp_bp_inval_start) add sp, sp, #(8 * 18) ENTRY(__psci_hyp_bp_inval_end) +ENTRY(__smccc_workaround_1_smc_start) + sub sp, sp, #(8 * 4) + stp x2, x3, [sp, #(8 * 0)] + stp x0, x1, [sp, #(8 * 2)] + mov w0, #ARM_SMCCC_ARCH_WORKAROUND_1_FID + ldp x2, x3, [sp, #(8 * 0)] + ldp x0, x1, [sp, #(8 * 2)] + add sp, sp, #(8 * 4) +ENTRY(__smccc_workaround_1_smc_end) + /* * Local variables: * mode: ASM diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c index 6704648b26..6557577bcb 100644 --- a/xen/arch/arm/cpuerrata.c +++ b/xen/arch/arm/cpuerrata.c @@ -147,6 +147,34 @@ install_bp_hardening_vec(const struct arm_cpu_capabilities *entry, return ret; } +extern char __smccc_workaround_1_smc_start[], __smccc_workaround_1_smc_end[]; + +static bool +check_smccc_arch_workaround_1(const struct arm_cpu_capabilities *entry) +{ + struct arm_smccc_res res; + + /* + * Enable callbacks are called on every CPU based on the + * capabilities. So double-check whether the CPU matches the + * entry. + */ + if ( !entry->matches(entry) ) + return false; + + if ( smccc_ver < SMCCC_VERSION(1, 1) ) + return false; + + arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FID, + ARM_SMCCC_ARCH_WORKAROUND_1_FID, &res); + if ( res.a0 != ARM_SMCCC_SUCCESS ) + return false; + + return install_bp_hardening_vec(entry,__smccc_workaround_1_smc_start, + __smccc_workaround_1_smc_end, + "call ARM_SMCCC_ARCH_WORKAROUND_1"); +} + extern char __psci_hyp_bp_inval_start[], __psci_hyp_bp_inval_end[]; static int enable_psci_bp_hardening(void *data) @@ -154,12 +182,14 @@ static int enable_psci_bp_hardening(void *data) bool ret = true; static bool warned = false; + if ( check_smccc_arch_workaround_1(data) ) + return 0; /* * The mitigation is using PSCI version function to invalidate the * branch predictor. This function is only available with PSCI 0.2 * and later. */ - if ( psci_ver >= PSCI_VERSION(0, 2) ) + else if ( psci_ver >= PSCI_VERSION(0, 2) ) ret = install_bp_hardening_vec(data, __psci_hyp_bp_inval_start, __psci_hyp_bp_inval_end, "call PSCI get version"); diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index 154772b728..8342cc33fe 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -261,6 +261,7 @@ struct arm_smccc_res { /* SMCCC error codes */ #define ARM_SMCCC_ERR_UNKNOWN_FUNCTION (-1) #define ARM_SMCCC_NOT_SUPPORTED (-1) +#define ARM_SMCCC_SUCCESS (0) /* SMCCC function identifier range which is reserved for existing APIs */ #define ARM_SMCCC_RESERVED_RANGE_START 0x0