From patchwork Thu Feb 15 15:02:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 128459 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1846907ljc; Thu, 15 Feb 2018 07:05:45 -0800 (PST) X-Google-Smtp-Source: AH8x2240FPGCrPinjWkI4H0QdlwsMpeq8b59axYcZrynn2L3WLXe04yvBxI0u61vAn/fKfsw9evK X-Received: by 10.36.58.135 with SMTP id m129mr3592157itm.52.1518707145129; Thu, 15 Feb 2018 07:05:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518707145; cv=none; d=google.com; s=arc-20160816; b=qNXYf4Eb/UV6hSYTLWfFJHVIU+TktnFZcRDzQWqjOwj3/u4Gm11RuVOaayg7Y9Gb2I f7rX1jGpgYgm11wMYr3IG/nDEe53xt9T6oYn3MIOR0ABezBarBpZ3gSbBjDmgFjflqHP WfMgaDcMHMFJrglBXNh4A9Ltqn30/pJoAHMiPkYod48M6Lb11uFH+cWwJLgJ+1B0A3pv 1eRE8vfEJuSbC1G6HPn7GHhGtSa6KukxiZJ/L0lLCxGKoz0rXaMOrwIA5wMklE7PTpCB a91eOPl7n17/8Y0/QIsrs9TuZQqAACj2JC4Szch9P+OFPNUfXU3BkMrS3xfE9L0ja+KM JT3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=XZh2KG7+YWE1uTP1an54DbDQaurz7Y3NGsUEbbWIgpw=; b=JXmslA+SIjzveRTayOUKWvJc4O0Wnm5icFxVtZUeDDtntit+1c/RPJcplMrA+x9c5o L5ZwHiGjC3ndycuj4wC+5AQHpqIJqyH+W3NtEm8GSXNHarZThcUVgOhebKbAILC1o4ap rHjtefXDZvZiyZCr9ZWsmefxzA31ze5YvD28AvPUsPhtddVgsQ29/Fzf8ELorzqnnhBO FiElYVe9itIwtLL7Onsul/sOeo3pDMidV7auCkLFyef5bzgE47Oj/cHTxalkLFALsUhd aAhqdhuMWNJc0cDmxdaaaBO+Pt1BLA++6hE7VNDJRJoECL4p6lNX+SJVuUOLP1nwd4Al D54w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id j204si881971iof.162.2018.02.15.07.05.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Feb 2018 07:05:45 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL4E-00027A-5k; Thu, 15 Feb 2018 15:03:22 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL4D-00020l-Ct for xen-devel@lists.xen.org; Thu, 15 Feb 2018 15:03:21 +0000 X-Inumbo-ID: 87810186-1261-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 87810186-1261-11e8-b9b1-635ca7ef6cff; Thu, 15 Feb 2018 15:04:33 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5976215BF; Thu, 15 Feb 2018 07:03:15 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4A51D3F41F; Thu, 15 Feb 2018 07:03:14 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 15 Feb 2018 15:02:43 +0000 Message-Id: <20180215150248.28922-13-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180215150248.28922-1-julien.grall@arm.com> References: <20180215150248.28922-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v3 12/17] xen/arm: vpsci: Remove parameter 'ver' from do_common_cpu X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Currently, the behavior of do_common_cpu will slightly change depending on the PSCI version passed in parameter. Looking at the code, more the specific 0.2 behavior could move out of the function or adapted for 0.1: - x0/r0 can be updated on PSCI 0.1 because general purpose registers are undefined upon CPU on. - PSCI 0.1 does not defined PSCI_ALREADY_ON. However, it would be safer to bail out if the CPU is already on. Based on this, the parameter 'ver' is removed and do_psci_cpu_on (implementation for PSCI 0.1) is adapted to avoid returning PSCI_ALREADY_ON. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Acked-by: Stefano Stabellini Reviewed-by: Andre Przywara --- The reviewed-by was kept despite move this patch towards the end of the series because there was no clash with the rest of the series. Changes in v2: - Move the patch towards the end of the series as not strictly necessary for SP2. - Add Volodymyr's reviewed-by --- xen/arch/arm/vpsci.c | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c index 19ee7caeb4..7ea3ea58e3 100644 --- a/xen/arch/arm/vpsci.c +++ b/xen/arch/arm/vpsci.c @@ -22,7 +22,7 @@ #include static int do_common_cpu_on(register_t target_cpu, register_t entry_point, - register_t context_id,int ver) + register_t context_id) { struct vcpu *v; struct domain *d = current->domain; @@ -40,8 +40,7 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point, if ( is_64bit_domain(d) && is_thumb ) return PSCI_INVALID_PARAMETERS; - if ( (ver == PSCI_VERSION(0, 2)) && - !test_bit(_VPF_down, &v->pause_flags) ) + if ( !test_bit(_VPF_down, &v->pause_flags) ) return PSCI_ALREADY_ON; if ( (ctxt = alloc_vcpu_guest_context()) == NULL ) @@ -55,18 +54,21 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point, ctxt->ttbr0 = 0; ctxt->ttbr1 = 0; ctxt->ttbcr = 0; /* Defined Reset Value */ + + /* + * x0/r0_usr are always updated because for PSCI 0.1 the general + * purpose registers are undefined upon CPU_on. + */ if ( is_32bit_domain(d) ) { ctxt->user_regs.cpsr = PSR_GUEST32_INIT; - if ( ver == PSCI_VERSION(0, 2) ) - ctxt->user_regs.r0_usr = context_id; + ctxt->user_regs.r0_usr = context_id; } #ifdef CONFIG_ARM_64 else { ctxt->user_regs.cpsr = PSR_GUEST64_INIT; - if ( ver == PSCI_VERSION(0, 2) ) - ctxt->user_regs.x0 = context_id; + ctxt->user_regs.x0 = context_id; } #endif @@ -93,7 +95,14 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point, static int32_t do_psci_cpu_on(uint32_t vcpuid, register_t entry_point) { - return do_common_cpu_on(vcpuid, entry_point, 0 , PSCI_VERSION(0, 1)); + int32_t ret; + + ret = do_common_cpu_on(vcpuid, entry_point, 0); + /* + * PSCI 0.1 does not define the return code PSCI_ALREADY_ON. + * Instead, return PSCI_INVALID_PARAMETERS. + */ + return (ret == PSCI_ALREADY_ON) ? PSCI_INVALID_PARAMETERS : ret; } static int32_t do_psci_cpu_off(uint32_t power_state) @@ -137,8 +146,7 @@ static int32_t do_psci_0_2_cpu_on(register_t target_cpu, register_t entry_point, register_t context_id) { - return do_common_cpu_on(target_cpu, entry_point, context_id, - PSCI_VERSION(0, 2)); + return do_common_cpu_on(target_cpu, entry_point, context_id); } static const unsigned long target_affinity_mask[] = {