From patchwork Thu Feb 15 15:02:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 128465 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1847024ljc; Thu, 15 Feb 2018 07:05:50 -0800 (PST) X-Google-Smtp-Source: AH8x227IBJz/kY7S2Z1W6dq/QyhpnpQX2aHuIZ+sQzrwROHNaukt4jPT5UcSPlhT/dOaYriasO66 X-Received: by 10.36.46.23 with SMTP id i23mr3775486ita.55.1518707150498; Thu, 15 Feb 2018 07:05:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518707150; cv=none; d=google.com; s=arc-20160816; b=G85QnbvF0RpFmqk8HSblplr4zRv3FCjzDMx2P94VQ76/uFGRIgmDji9sXLI24Xtr0d 3USAMJLl/QtkZAq3qvcgUz8dEyWg/Ha6H0vaDOz5D40s0nj+2FaTxFjEIusPUezMcC2O gzQlfozNsyk1OI6vRNq5aQt8F7Ejo2fPsoyMOlA6wL9xRB2I+S3EomoJPDklIkN7J6Dy KgohddHuBshTzJ+kCB5f5T5L4tD74R7MdrSs4YXQn334eA9X3QLyERxNgzNOxTWkQrsK a1oTMusiya1/Fj1J5IfMTgeA7dGrKhxdDd9+Y/R7SHiTzFVEUdtp7S/SdbCqW0TJNfKZ XGQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=PrFouUW6WxyPfPQX1gemJxx+wmbais6t54EO7G2KgwE=; b=kVrQo7srMuDfGKzjBgpBYi5f7IQAB0kuVXkk2WAhUo2zZNYbRfjTcqtTlWOubebhmi Swa3KK0gdOMcV1OrOzcpa9TxgpFzCgVV+OB7/AUbWiDq4PLbx8twg2MV6atmnPlm3jdJ Pyv33tG8XRixWmJx3EageK+3Qq1Ij0ggsP1HJrbi5tHoyq2i2HIqJvbedfM1albeW1VD O/lNhQnJa466xiQkdL7IdNzUrIxn2t/6Hrq7rPpmpBT7Ux0vvllva93X/beVpuwBkloG tn8jPgrlgUHo6uVGFkXBz1xZdrrnGdPLv4hJH3s4SRnofLLWdw0S887IzFbKGQ8ug8qR C92Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id c63si1776135itb.42.2018.02.15.07.05.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Feb 2018 07:05:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL3x-0001ww-Ul; Thu, 15 Feb 2018 15:03:05 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1emL3w-0001wi-Ru for xen-devel@lists.xen.org; Thu, 15 Feb 2018 15:03:04 +0000 X-Inumbo-ID: 3bcf66c7-1261-11e8-ba59-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 3bcf66c7-1261-11e8-ba59-bc764e045a96; Thu, 15 Feb 2018 16:02:26 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 77CAD15BF; Thu, 15 Feb 2018 07:03:03 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 67D913F41F; Thu, 15 Feb 2018 07:03:02 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 15 Feb 2018 15:02:34 +0000 Message-Id: <20180215150248.28922-4-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180215150248.28922-1-julien.grall@arm.com> References: <20180215150248.28922-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v3 03/17] xen/arm: vsmc: Implement SMCCC_ARCH_WORKAROUND_1 BP hardening support X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" SMCCC 1.1 offers firmware-based CPU workarounds. In particular, SMCCC_ARCH_WORKAROUND_1 provides BP hardening for variant 2 of XSA-254 (CVE-2017-5715). If the hypervisor has some mitigation for this issue, report that we deal with it using SMCCC_ARCH_WORKAROUND_1, as we apply the hypervisor workaround on every guest exit. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Acked-by: Stefano Stabellini Reviewed-by: Andre Przywara --- Changes in v3: - Fix minor conflict during rebase Changes in v2: - Add Volodymyr's reviewed-by --- xen/arch/arm/vsmc.c | 22 ++++++++++++++++++++-- xen/include/asm-arm/smccc.h | 6 ++++++ 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/vsmc.c b/xen/arch/arm/vsmc.c index 7ec492741b..40a80d5760 100644 --- a/xen/arch/arm/vsmc.c +++ b/xen/arch/arm/vsmc.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -93,8 +94,25 @@ static bool handle_arch(struct cpu_user_regs *regs) return true; case ARM_SMCCC_ARCH_FEATURES_FID: - /* Nothing supported yet */ - set_user_reg(regs, 0, ARM_SMCCC_NOT_SUPPORTED); + { + uint32_t arch_func_id = get_user_reg(regs, 1); + int ret = ARM_SMCCC_NOT_SUPPORTED; + + switch ( arch_func_id ) + { + case ARM_SMCCC_ARCH_WORKAROUND_1_FID: + if ( cpus_have_cap(ARM_HARDEN_BRANCH_PREDICTOR) ) + ret = 0; + break; + } + + set_user_reg(regs, 0, ret); + + return true; + } + + case ARM_SMCCC_ARCH_WORKAROUND_1_FID: + /* No return value */ return true; } diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index 629cc5150b..2951caa49d 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -115,6 +115,12 @@ static inline uint32_t smccc_get_owner(register_t funcid) ARM_SMCCC_OWNER_ARCH, \ 0x1) +#define ARM_SMCCC_ARCH_WORKAROUND_1_FID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_CONV_32, \ + ARM_SMCCC_OWNER_ARCH, \ + 0x8000) + /* SMCCC error codes */ #define ARM_SMCCC_ERR_UNKNOWN_FUNCTION (-1) #define ARM_SMCCC_NOT_SUPPORTED (-1)