From patchwork Fri Feb 23 18:57:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129488 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp984771edc; Fri, 23 Feb 2018 10:59:55 -0800 (PST) X-Google-Smtp-Source: AH8x227ygc4Z3CxEo6wqVZRQ/U/eaBN8GlYUVvEeSF3v+8BZeYvhMYhzXw7RpBC5Rx6P5L24CCho X-Received: by 10.36.68.214 with SMTP id o205mr3399604ita.49.1519412395556; Fri, 23 Feb 2018 10:59:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519412395; cv=none; d=google.com; s=arc-20160816; b=fJGmeOw7/ofsuXJ/SFkf7AW2cK9DCEt33a4AhMoYnxChhmvcn5TmBA+z1TByPJy2JU /Qr4c9RGYerbvAl7UMr1dDpTKIX8jWPW41Bfw34p36K1wpfIwA4nZdT6/H1ujlAp9BHH JoaOK1WEa2t9DFJ2AtWKmF80CSgUFNBWeSqC/usJYnbiNoPJfvOm7kH3S6f+kIZFkhjE QQWeFNCs6Ash+DBETq/L2sygj17yZR7+lzFQjX07G0aeO0rw9XmmZgSgDTJD/ER2cgow ZLhytI2qwZ9CsbKSaAPrPsqACUyRSkUslA+CXEvTflEAsHoFlxbp1QdIfaPuqKr1j88q 0Fsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=ZgGCIv4UMySKAXi0fQJavGU/hzH+RKJWEdEIyP1zofY=; b=BSJe7PVb9OP2zrcnkMUFJaZCZD5Dw4UAit1XPiEZgdtCcd3mvIjRbFhbA1hJBGPuo4 DlkbMcdBh7nzYO1rYwToT2LxT+WaWF08Mm1m3+gZItVUm1Y/KIxg7w4VjE35+dYh+nWX zLcUgRK0LyLrYMyCsPkD6aqJWNZpahupqes2DJQc0muUhE2NEDFQl6qY1TDgN5TNgdZP u75wWt65d4zv0iInuK2/FgDtVb1asfj+jdbgIU1abihrZ2kZ1IAH/WrlMgLk7gyQ8De0 1PdqZRmbiRE0uQSZlhgFSvtyVtbidHo5IoLDNOmNdzW27nQ/0hwCP82aGU00HdpSTwPT JJIw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id x196si1581058itb.101.2018.02.23.10.59.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 10:59:55 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXk-0003Ej-Bn; Fri, 23 Feb 2018 18:58:04 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXi-0003Ca-SS for xen-devel@lists.xen.org; Fri, 23 Feb 2018 18:58:02 +0000 X-Inumbo-ID: 5b1739c6-18cb-11e8-ba59-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 5b1739c6-18cb-11e8-ba59-bc764e045a96; Fri, 23 Feb 2018 19:57:12 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3AFBA80D; Fri, 23 Feb 2018 10:58:02 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0567E3F25C; Fri, 23 Feb 2018 10:58:00 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 18:57:29 +0000 Message-Id: <20180223185729.8780-19-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223185729.8780-1-julien.grall@arm.com> References: <20180223185729.8780-1-julien.grall@arm.com> Cc: Andre Przywara , Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v5 18/18] xen/arm: vpsci: Rework the logic to start AArch32 vCPU in Thumb mode X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" 32-bit domain is able to select the instruction (ARM vs Thumb) to use when boot a new vCPU via CPU_ON. This is indicated via bit[0] of the entry point address (see "T32 support" in PSCI v1.1 DEN0022D). bit[0] must be cleared when setting the PC. At the moment, Xen is setting the CPSR.T but never clear bit[0]. Clear it to match the specification. At the same time, slighlty rework the code to make clear thumb is only for 32-bit domain. Lastly, take the opportunity to switch is_thumb from int to bool. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini Reviewed-by: Andre Przywara --- Changes in v4: - Add Stefano's reviewed-by - Add Andre's reviewed-by Changes in v3: - Patch added --- xen/arch/arm/vpsci.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c index 1729f7071e..9f4e5b8844 100644 --- a/xen/arch/arm/vpsci.c +++ b/xen/arch/arm/vpsci.c @@ -28,7 +28,7 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point, struct domain *d = current->domain; struct vcpu_guest_context *ctxt; int rc; - int is_thumb = entry_point & 1; + bool is_thumb = entry_point & 1; register_t vcpuid; vcpuid = vaffinity_to_vcpuid(target_cpu); @@ -62,6 +62,13 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point, if ( is_32bit_domain(d) ) { ctxt->user_regs.cpsr = PSR_GUEST32_INIT; + /* Start the VCPU with THUMB set if it's requested by the kernel */ + if ( is_thumb ) + { + ctxt->user_regs.cpsr |= PSR_THUMB; + ctxt->user_regs.pc64 &= ~(u64)1; + } + ctxt->user_regs.r0_usr = context_id; } #ifdef CONFIG_ARM_64 @@ -71,10 +78,6 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point, ctxt->user_regs.x0 = context_id; } #endif - - /* Start the VCPU with THUMB set if it's requested by the kernel */ - if ( is_thumb ) - ctxt->user_regs.cpsr |= PSR_THUMB; ctxt->flags = VGCF_online; domain_lock(d);