From patchwork Tue Oct 23 18:17:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 149462 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1032232ljp; Tue, 23 Oct 2018 11:19:36 -0700 (PDT) X-Google-Smtp-Source: ACcGV60cgC7T0Bag3WhCu8+Rl23Ck1UrQb24hCGgNRC3sxLW0LWH7M5TQNzfjg9Y/DLgANpN7qpl X-Received: by 2002:a25:b94a:: with SMTP id s10-v6mr37108589ybm.130.1540318776340; Tue, 23 Oct 2018 11:19:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540318776; cv=none; d=google.com; s=arc-20160816; b=kn2BSfW457zTlzKzOGrKRIn/TH3N7q+xtl3FwGM95B00FBdiFfIbF75vqa94Tz2N0y 2wbIHhWCZT9vF9kYQxe6J0pnUfGNgPFV4kZI3gOy/bC+W7FXvM9eBft11DGbt5gzhOzN 13pplVH1eClTHYAI/4LLA5NhfoWoYcJgYfA+Olq3UONQeCQrZfARZ120og76HigUwfTL vQkBCm7uxdbJO/EYWlB4vbtP7PyuyK92O4CNEbUFh9Z7otANr4U8HJGtNcbr6/M/mqDc ofjAiKdt2JjCKOd7/WkEbB4lePaTGjTIn8eY4mBldm+x3v17Bzl50y1jnWwtSp59m4IN xlkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=1lwhZ29RAETizYYpikyyn2KC4scGM1EuddCNav2/QD0=; b=cO+72rCjWQGjsobfN4+Ydlx7Je7HeRc2xHNedlz3GjflpXF9ruquccPILc8x7XdntE XAhP0R8FdEMDOhfYE4v89RN+nMC5PlATRx4fO6X23NQt8saz6iHDPr1hsF8kLpTaj4dF HGT5UdAk0dNrd9v5EZonVLgmVarx6yGfUBeUVezTep8V1kj7nbgO5FQmKftDtWFkviG5 5NWnDVm/EM2avutrnZRQi+KegdtDEGoSuPr7qOxbsYARJ05ShFDyw3RNrNfr6Ec9Bxl3 zoBRRYc5h1uvsfkD0/AF5eFdDzzN55S5VSRnv+SCm4z2mOWCyi4v78Vrci4KNbgJ/8sJ 4+vQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id 85-v6si1351364ywp.130.2018.10.23.11.19.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Oct 2018 11:19:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gF1F3-0006Of-RF; Tue, 23 Oct 2018 18:17:21 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gF1F2-0006OV-Lv for xen-devel@lists.xen.org; Tue, 23 Oct 2018 18:17:20 +0000 X-Inumbo-ID: 16127088-d6f0-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 16127088-d6f0-11e8-a6a9-d7ebe60f679a; Tue, 23 Oct 2018 18:18:48 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 712AEEBD; Tue, 23 Oct 2018 11:17:18 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8604C3F5D3; Tue, 23 Oct 2018 11:17:17 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Tue, 23 Oct 2018 19:17:06 +0100 Message-Id: <20181023181709.11883-2-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181023181709.11883-1-julien.grall@arm.com> References: <20181023181709.11883-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 1/4] xen/arm: gic: Ensure we have an ISB between ack and do_IRQ() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Devices that expose their interrupt status registers via system registers (e.g. Statistical profiling, CPU PMU, DynamIQ PMU, arch timer, vgic (although unused by Linux), ...) rely on a context synchronising operation on the CPU to ensure that the updated status register is visible to the CPU when handling the interrupt. This usually happens as a result of taking the IRQ exception in the first place, but there are two race scenarios where this isn't the case. For example, let's say we have two peripherals (X and Y), where Y uses a system register for its interrupt status. Case 1: 1. CPU takes an IRQ exception as a result of X raising an interrupt 2. Y then raises its interrupt line, but the update to its system register is not yet visible to the CPU 3. The GIC decides to expose Y's interrupt number first in the Ack register 4. The CPU runs the IRQ handler for Y, but the status register is stale Case 2: 1. CPU takes an IRQ exception as a result of X raising an interrupt 2. CPU reads the interrupt number for X from the Ack register and runs its IRQ handler 3. Y raises its interrupt line and the Ack register is updated, but again, the update to its system register is not yet visible to the CPU. 4. Since the GIC drivers poll the Ack register, we read Y's interrupt number and run its handler without a context synchronisation operation, therefore seeing the stale register value. In either case, we run the risk of missing an IRQ. This patch solves the problem by ensuring that we execute an ISB in the GIC drivers prior to invoking the interrupt handler. Based on Linux commit 39a06b67c2c1256bcf2361a1f67d2529f70ab206 "irqchip/gic: Ensure we have an ISB between ack and ->handle_irq". Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov Acked-by: Stefano Stabellini --- This patch is a candidate for backporting up to Xen 4.9. --- xen/arch/arm/gic.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 8d7e491060..305fbd66dd 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -388,12 +388,14 @@ void gic_interrupt(struct cpu_user_regs *regs, int is_fiq) if ( likely(irq >= 16 && irq < 1020) ) { local_irq_enable(); + isb(); do_IRQ(regs, irq, is_fiq); local_irq_disable(); } else if ( is_lpi(irq) ) { local_irq_enable(); + isb(); gic_hw_ops->do_LPI(irq); local_irq_disable(); }