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[192.237.175.120]) by mx.google.com with ESMTPS id d186-v6si1337590ywe.352.2018.10.23.11.19.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Oct 2018 11:19:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gF1F7-0006Py-6O; Tue, 23 Oct 2018 18:17:25 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gF1F5-0006PD-90 for xen-devel@lists.xen.org; Tue, 23 Oct 2018 18:17:23 +0000 X-Inumbo-ID: 183798cf-d6f0-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 183798cf-d6f0-11e8-a6a9-d7ebe60f679a; Tue, 23 Oct 2018 18:18:52 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F28F6EBD; Tue, 23 Oct 2018 11:17:21 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 133C83F5D3; Tue, 23 Oct 2018 11:17:20 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Tue, 23 Oct 2018 19:17:09 +0100 Message-Id: <20181023181709.11883-5-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181023181709.11883-1-julien.grall@arm.com> References: <20181023181709.11883-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 4/4] xen/arm: gic: Relax barrier when sending an SGI X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" When sending an SGI to another CPU, we require a barrier to ensure that any pending stores to normal memory are made visible to the recipient before the interrupt arrives. For GICv2, rather than using dsb(sy) before writel_gicd, we can instead use dsb(ishst), since we just need to ensure that any pending normal writes are visible within the inner-shareable domain before we poke the GIC. With this observation, we can then further weaken the barrier to a dmb(ishst), since other CPUs in the inner-shareable domain must observe the write to the distributor before the SGI is generated. A DMB instruction can be used to ensure the relative order of only memory accesses before and after the barrier. Since writes to system registers are not memory operations, barrier DMB is not sufficient for observalibility of memory accesses that occur before ICC_SGI1R_EL1 (GICv3). For GICv3, a DSB instruction ensures that no instructions that appear in program order after the DSB instruction, can execute until the DSB instruction has completed. Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov Reviewed-by: Stefano Stabellini --- xen/arch/arm/gic-v2.c | 6 ++++++ xen/arch/arm/gic-v3.c | 6 ++++++ xen/arch/arm/gic.c | 18 ------------------ 3 files changed, 12 insertions(+), 18 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index e7eb01f30a..1a744c576f 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -455,6 +455,12 @@ static void gicv2_send_SGI(enum gic_sgi sgi, enum gic_sgi_mode irqmode, unsigned int mask = 0; cpumask_t online_mask; + /* + * Ensure that stores to Normal memory are visible to the other CPUs + * before they observe us issuing the IPI. + */ + dmb(ishst); + switch ( irqmode ) { case SGI_TARGET_OTHERS: diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 2952335d05..a0a1a45ba7 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -986,6 +986,12 @@ static void gicv3_send_sgi_list(enum gic_sgi sgi, const cpumask_t *cpumask) static void gicv3_send_sgi(enum gic_sgi sgi, enum gic_sgi_mode mode, const cpumask_t *cpumask) { + /* + * Ensure that stores to Normal memory are visible to the other CPUs + * before issuing the IPI. + */ + wmb(); + switch ( mode ) { case SGI_TARGET_OTHERS: diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 0108e9603c..077b941b79 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -300,12 +300,6 @@ void send_SGI_mask(const cpumask_t *cpumask, enum gic_sgi sgi) { ASSERT(sgi < 16); /* There are only 16 SGIs */ - /* - * Ensure that stores to Normal memory are visible to the other CPUs - * before issuing the IPI. - * Matches the read barrier in do_sgi. - */ - dsb(sy); gic_hw_ops->send_SGI(sgi, SGI_TARGET_LIST, cpumask); } @@ -318,12 +312,6 @@ void send_SGI_self(enum gic_sgi sgi) { ASSERT(sgi < 16); /* There are only 16 SGIs */ - /* - * Ensure that stores to Normal memory are visible to the other CPUs - * before issuing the IPI. - * Matches the read barrier in do_sgi. - */ - dsb(sy); gic_hw_ops->send_SGI(sgi, SGI_TARGET_SELF, NULL); } @@ -331,12 +319,6 @@ void send_SGI_allbutself(enum gic_sgi sgi) { ASSERT(sgi < 16); /* There are only 16 SGIs */ - /* - * Ensure that stores to Normal memory are visible to the other CPUs - * before issuing the IPI. - * Matches the read barrier in do_sgi. - */ - dsb(sy); gic_hw_ops->send_SGI(sgi, SGI_TARGET_OTHERS, NULL); }