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[50.57.142.19]) by mx.google.com with ESMTPS id u7si501017vcn.37.2014.02.26.11.39.22 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 26 Feb 2014 11:39:22 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xen.org designates 50.57.142.19 as permitted sender) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WIkHm-0001eh-CC; Wed, 26 Feb 2014 19:36:54 +0000 Received: from mail6.bemta4.messagelabs.com ([85.158.143.247]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WIkHk-0001ec-QZ for xen-devel@lists.xensource.com; Wed, 26 Feb 2014 19:36:53 +0000 Received: from [85.158.143.35:9462] by server-3.bemta-4.messagelabs.com id D3/4D-11539-4524E035; Wed, 26 Feb 2014 19:36:52 +0000 X-Env-Sender: Stefano.Stabellini@citrix.com X-Msg-Ref: server-4.tower-21.messagelabs.com!1393443409!8550907!1 X-Originating-IP: [66.165.176.89] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni44OSA9PiAyMDMwMDc=\n X-StarScan-Received: X-StarScan-Version: 6.9.16; banners=-,-,- X-VirusChecked: Checked Received: (qmail 12434 invoked from network); 26 Feb 2014 19:36:51 -0000 Received: from smtp.citrix.com (HELO SMTP.CITRIX.COM) (66.165.176.89) by server-4.tower-21.messagelabs.com with RC4-SHA encrypted SMTP; 26 Feb 2014 19:36:51 -0000 X-IronPort-AV: E=Sophos;i="4.97,549,1389744000"; d="scan'208";a="106046541" Received: from accessns.citrite.net (HELO FTLPEX01CL03.citrite.net) ([10.9.154.239]) by FTLPIPO01.CITRIX.COM with ESMTP; 26 Feb 2014 19:36:49 +0000 Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.80) with Microsoft SMTP Server id 14.2.342.4; Wed, 26 Feb 2014 14:36:49 -0500 Received: from kaball.uk.xensource.com ([10.80.2.59]) by ukmail1.uk.xensource.com with esmtp (Exim 4.69) (envelope-from ) id 1WIkHg-00059U-5E; Wed, 26 Feb 2014 19:36:48 +0000 Date: Wed, 26 Feb 2014 19:36:43 +0000 From: Stefano Stabellini X-X-Sender: sstabellini@kaball.uk.xensource.com To: Stefano Stabellini In-Reply-To: <1393439997-26936-11-git-send-email-stefano.stabellini@eu.citrix.com> Message-ID: References: <1393439997-26936-11-git-send-email-stefano.stabellini@eu.citrix.com> User-Agent: Alpine 2.02 (DEB 1266 2009-07-14) MIME-Version: 1.0 X-DLP: MIA2 Cc: julien.grall@citrix.com, jtd@galois.com, xen-devel@lists.xensource.com, Ian.Campbell@citrix.com Subject: Re: [Xen-devel] [PATCH-4.5 v3 11/12] xen/arm: gic_events_need_delivery and irq priorities X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: stefano.stabellini@eu.citrix.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.180 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: On Wed, 26 Feb 2014, Stefano Stabellini wrote: > gic_events_need_delivery should only return positive if an outstanding > pending irq has an higher priority than the currently active irq and the > priority mask. > Rewrite the function by going through the priority ordered inflight and > lr_queue lists. > > In gic_restore_pending_irqs replace lower priority pending (and not > active) irqs in GICH_LRs with higher priority irqs if no more GICH_LRs > are available. > > Signed-off-by: Stefano Stabellini [snip] > @@ -779,8 +806,38 @@ void gic_clear_pending_irqs(struct vcpu *v) > > int gic_events_need_delivery(void) > { > - return (!list_empty(¤t->arch.vgic.lr_pending) || > - this_cpu(lr_mask)); > + int mask_priority, lrs = nr_lrs; > + int max_priority = 0xff, active_priority = 0xff; > + struct vcpu *v = current; > + struct pending_irq *p; > + unsigned long flags; > + > + mask_priority = (GICH[GICH_VMCR] >> GICH_VMCR_PRIORITY_SHIFT) & GICH_VMCR_PRIORITY_MASK; > + > + spin_lock_irqsave(&v->arch.vgic.lock, flags); > + > + list_for_each_entry( p, &v->arch.vgic.lr_pending, lr_queue ) > + { Unfortunately I sent the wrong version of this patch. We should be going through the inflight list here, not the lr_pending list: list_for_each_entry( p, &v->arch.vgic.inflight_irqs, inflight ) I also added a check for GIC_IRQ_GUEST_ENABLED. I pushed the full series with this small fix to: git://xenbits.xen.org/people/sstabellini/xen-unstable.git no_maintenance_interrupts-v3.1 I am also appending the newer version here. commit cfddc7eb3a7d4649ceacdf89609a86d826773e9e Author: Stefano Stabellini Date: Wed Feb 26 19:21:35 2014 +0000 xen/arm: gic_events_need_delivery and irq priorities gic_events_need_delivery should only return positive if an outstanding pending irq has an higher priority than the currently active irq and the priority mask. Rewrite the function by going through the priority ordered inflight and lr_queue lists. In gic_restore_pending_irqs replace lower priority pending (and not active) irqs in GICH_LRs with higher priority irqs if no more GICH_LRs are available. Signed-off-by: Stefano Stabellini --- Changes in v4: - in gic_events_need_delivery go through inflight_irqs and only consider enabled irqs. diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 296d9a7..d2e23a9 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -709,6 +709,7 @@ static void _gic_clear_lr(struct vcpu *v, int i) p = irq_to_pending(v, irq); if ( lr & GICH_LR_ACTIVE ) { + set_bit(GIC_IRQ_GUEST_ACTIVE, &p->status); /* HW interrupts cannot be ACTIVE and PENDING */ if ( p->desc == NULL && test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) && @@ -723,6 +724,7 @@ static void _gic_clear_lr(struct vcpu *v, int i) if ( p->desc != NULL ) p->desc->status &= ~IRQ_INPROGRESS; clear_bit(GIC_IRQ_GUEST_VISIBLE, &p->status); + clear_bit(GIC_IRQ_GUEST_ACTIVE, &p->status); p->lr = nr_lrs; if ( test_bit(GIC_IRQ_GUEST_PENDING, &p->status) && test_bit(GIC_IRQ_GUEST_ENABLED, &p->status)) @@ -750,22 +752,47 @@ void gic_clear_lrs(struct vcpu *v) static void gic_restore_pending_irqs(struct vcpu *v) { - int i; - struct pending_irq *p, *t; + int i = 0, lrs = nr_lrs; + struct pending_irq *p, *t, *p_r; unsigned long flags; + if ( list_empty(&v->arch.vgic.lr_pending) ) + return; + + spin_lock_irqsave(&v->arch.vgic.lock, flags); + + p_r = list_entry(v->arch.vgic.inflight_irqs.prev, + typeof(*p_r), inflight); list_for_each_entry_safe ( p, t, &v->arch.vgic.lr_pending, lr_queue ) { i = find_first_zero_bit(&this_cpu(lr_mask), nr_lrs); - if ( i >= nr_lrs ) return; + if ( i >= nr_lrs ) + { + while ( !test_bit(GIC_IRQ_GUEST_VISIBLE, &p_r->status) || + test_bit(GIC_IRQ_GUEST_ACTIVE, &p_r->status) ) + { + p_r = list_entry(p_r->inflight.prev, typeof(*p_r), inflight); + if ( &p_r->inflight == p->inflight.next ) + goto out; + } + i = p_r->lr; + p_r->lr = nr_lrs; + set_bit(GIC_IRQ_GUEST_PENDING, &p_r->status); + clear_bit(GIC_IRQ_GUEST_VISIBLE, &p_r->status); + gic_add_to_lr_pending(v, p_r->irq, p_r->priority); + } - spin_lock_irqsave(&v->arch.vgic.lock, flags); gic_set_lr(v, i, p->irq, GICH_LR_PENDING, p->priority); list_del_init(&p->lr_queue); set_bit(i, &this_cpu(lr_mask)); - spin_unlock_irqrestore(&v->arch.vgic.lock, flags); + + lrs--; + if ( lrs == 0 ) + break; } +out: + spin_unlock_irqrestore(&v->arch.vgic.lock, flags); } void gic_clear_pending_irqs(struct vcpu *v) @@ -779,8 +806,38 @@ void gic_clear_pending_irqs(struct vcpu *v) int gic_events_need_delivery(void) { - return (!list_empty(¤t->arch.vgic.lr_pending) || - this_cpu(lr_mask)); + int mask_priority, lrs = nr_lrs; + int max_priority = 0xff, active_priority = 0xff; + struct vcpu *v = current; + struct pending_irq *p; + unsigned long flags; + + mask_priority = (GICH[GICH_VMCR] >> GICH_VMCR_PRIORITY_SHIFT) & GICH_VMCR_PRIORITY_MASK; + + spin_lock_irqsave(&v->arch.vgic.lock, flags); + + list_for_each_entry( p, &v->arch.vgic.inflight_irqs, inflight ) + { + if ( test_bit(GIC_IRQ_GUEST_ACTIVE, &p->status) ) + { + if ( p->priority < active_priority ) + active_priority = p->priority; + } else if ( test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) ) { + if ( p->priority < max_priority ) + max_priority = p->priority; + } + lrs--; + if ( lrs == 0 ) + break; + } + + spin_unlock_irqrestore(&v->arch.vgic.lock, flags); + + if ( max_priority < active_priority && + (max_priority >> 3) < mask_priority ) + return 1; + else + return 0; } void gic_inject(void) diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index 7b636c8..86cb361 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -56,8 +56,9 @@ struct pending_irq * */ #define GIC_IRQ_GUEST_PENDING 0 -#define GIC_IRQ_GUEST_VISIBLE 1 -#define GIC_IRQ_GUEST_ENABLED 2 +#define GIC_IRQ_GUEST_ACTIVE 1 +#define GIC_IRQ_GUEST_VISIBLE 2 +#define GIC_IRQ_GUEST_ENABLED 3 unsigned long status; uint8_t lr; struct irq_desc *desc; /* only set it the irq corresponds to a physical irq */ diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 5a9dc77..5d8f7f1 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -129,6 +129,9 @@ #define GICH_LR_CPUID_SHIFT 9 #define GICH_VTR_NRLRGS 0x3f +#define GICH_VMCR_PRIORITY_MASK 0x1f +#define GICH_VMCR_PRIORITY_SHIFT 27 + /* * The minimum GICC_BPR is required to be in the range 0-3. We set * GICC_BPR to 0 but we must expect that it might be 3. This means we