From patchwork Wed Mar 16 16:17:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivasa Rao Mandadapu X-Patchwork-Id: 551843 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8053CC433F5 for ; Wed, 16 Mar 2022 16:19:35 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id BEADA16FF; Wed, 16 Mar 2022 17:18:43 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz BEADA16FF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1647447573; bh=HSjIFBA0NEB+IiUlsgxwaJuvrNUUtYH5i8FRAt8mxHs=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=ALZQgIl3ppo4WyMNshc8/Q6N+k0Jnjyz50FcSddo6OeMvPgOdIuKHgHP+z+dk24tu Q5wHTiEMCKfL35MFSWGcrZveUNJPxVeURB1sCDYehDZmZD+Bq2litGZgJ2CsuGhSN1 L0UF7DzgK008bHgH6dz4UTV+PQQ8qfivXyZdLh0A= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id BADA5F80510; Wed, 16 Mar 2022 17:18:03 +0100 (CET) Received: by alsa1.perex.cz (Postfix, from userid 50401) id EAB74F804E6; Wed, 16 Mar 2022 17:18:02 +0100 (CET) Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) (using TLSv1.2 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 0D965F804E6 for ; Wed, 16 Mar 2022 17:17:55 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 0D965F804E6 Authentication-Results: alsa1.perex.cz; dkim=pass (1024-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="QU9Rdn3d" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1647447481; x=1678983481; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=As1X0P/G4QwXKGqgTUAbh2m46WDe6bYCw7umSlOuyHc=; b=QU9Rdn3dBYe9TV9nf79ytDgX37b+632bHZdzIQUYKtWrVWPQ2GWI+oxz ywUoq0ckDzSyHRs1bjOOtHpY7y9cHZwnRIhyd0+b6EKJ7g8EFhtBhMyrB YWw4o2+bWs5TZOmstJywiLQCjOlzQinGS9aj51CVpn6yZq4AJd7+hyibW 0=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 16 Mar 2022 09:17:54 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2022 09:17:53 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 09:17:52 -0700 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 16 Mar 2022 09:17:46 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , , , , , , , , Linus Walleij , Subject: [PATCH v12 2/7] dt-bindings: pinctrl: qcom: Add sc7280 lpass lpi pinctrl bindings Date: Wed, 16 Mar 2022 21:47:01 +0530 Message-ID: <1647447426-23425-3-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647447426-23425-1-git-send-email-quic_srivasam@quicinc.com> References: <1647447426-23425-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Cc: Venkata Prasad Potturu , Srinivasa Rao Mandadapu X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Add device tree binding Documentation details for Qualcomm SC7280 LPASS LPI pinctrl driver. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu Reviewed-by: Rob Herring Reviewed-by: Stephen Boyd --- .../pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml | 115 +++++++++++++++++++++ 1 file changed, 115 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml new file mode 100644 index 0000000..d32ee32 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS) + Low Power Island (LPI) TLMM block + +maintainers: + - Srinivasa Rao Mandadapu + - Srinivas Kandagatla + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + LPASS LPI IP on most Qualcomm SoCs + +properties: + compatible: + const: qcom,sc7280-lpass-lpi-pinctrl + + reg: + minItems: 2 + maxItems: 2 + + gpio-controller: true + + '#gpio-cells': + description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + +#PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: "/schemas/pinctrl/pincfg-node.yaml" + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9])$" + minItems: 1 + maxItems: 15 + + function: + enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws, + qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk, + dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data, + i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk, + dmic3_data, i2s2_data ] + description: + Specify the alternative function to be configured for the specified + pins. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + slew-rate: + enum: [0, 1, 2, 3] + default: 0 + description: | + 0: No adjustments + 1: Higher Slew rate (faster edges) + 2: Lower Slew rate (slower edges) + 3: Reserved (No adjustments) + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + output-high: true + + output-low: true + + required: + - pins + - function + + additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + lpass_tlmm: pinctrl@33c0000 { + compatible = "qcom,sc7280-lpass-lpi-pinctrl"; + reg = <0x33c0000 0x20000>, + <0x3550000 0x10000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 15>; + };