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[6/6] ASoC: dt-bindings: fsl-sai: Add two PLL clock source

Message ID 1656567554-32122-7-git-send-email-shengjiu.wang@nxp.com
State Accepted
Commit 6c06ad34eda9e1990313ff80999e1a75a02fa1c0
Headers show
Series Add support of two Audio PLL source | expand

Commit Message

Shengjiu Wang June 30, 2022, 5:39 a.m. UTC
Add two PLL clock source, they are the parent clocks of root clock
one is for 8kHz series rates, another one is for 11kHz series rates.
They are optional clocks, if there are such clocks, then driver
can switch between them for supporting more accurate rates.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
 Documentation/devicetree/bindings/sound/fsl-sai.txt | 3 +++
 1 file changed, 3 insertions(+)
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diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt
index 4c66e6a1a533..fbdefc3fade7 100644
--- a/Documentation/devicetree/bindings/sound/fsl-sai.txt
+++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt
@@ -21,6 +21,9 @@  Required properties:
   - clock-names		: Must include the "bus" for register access and
 			  "mclk1", "mclk2", "mclk3" for bit clock and frame
 			  clock providing.
+                          "pll8k", "pll11k" are optional, they are the clock
+                          source for root clock, one is for 8kHz series rates
+                          another one is for 11kHz series rates.
   - dmas		: Generic dma devicetree binding as described in