From patchwork Tue Mar 7 14:15:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Herve Codina X-Patchwork-Id: 660481 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AEC71C678D4 for ; Tue, 7 Mar 2023 14:17:43 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 7368C1490; Tue, 7 Mar 2023 15:16:51 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 7368C1490 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1678198661; bh=/9Zd3MTv3rJFHxBpTqTSfU1u802HF8QnrfFboPggdK8=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Archive: List-Help:List-Owner:List-Post:List-Subscribe:List-Unsubscribe: From:Reply-To:Cc:From; b=UGgZwe/Gf06alUWmKi894E9lwy5f7raOL17wITpq91cCEziPBOsEqcuV/6S8o6294 AZgQAfq2xtErBX3CSWUpVvBKJGfif+UFOMAagbLI8mxCoAsDYDwrvf7MCX3Ajvg/sn yWA5PCZzbbVMiXlgtUSDXWA8XC+0Xa2DlevRBrGE= Received: from mailman-core.alsa-project.org (mailman-core.alsa-project.org [10.254.200.10]) by alsa1.perex.cz (Postfix) with ESMTP id 16F09F80548; Tue, 7 Mar 2023 15:15:52 +0100 (CET) To: Herve Codina , Li Yang , Rob Herring , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Christophe Leroy , Michael Ellerman , Nicholas Piggin , Qiang Zhao , Jaroslav Kysela , Takashi Iwai , Shengjiu Wang , Xiubo Li , Fabio Estevam , Nicolin Chen Subject: [PATCH 3/3] soc: fsl: cpm1: qmc: Fix assigned timeslot masks Date: Tue, 7 Mar 2023 15:15:03 +0100 In-Reply-To: <20230307141503.159766-1-herve.codina@bootlin.com> References: <20230307141503.159766-1-herve.codina@bootlin.com> X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-alsa-devel.alsa-project.org-0; header-match-alsa-devel.alsa-project.org-1; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header X-Mailman-Version: 3.3.8 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <167819855177.26.11163930602844526001@mailman-core.alsa-project.org> X-Patchwork-Original-From: Herve Codina via Alsa-devel From: Herve Codina Reply-To: Herve Codina Cc: linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, Thomas Petazzoni Content-Disposition: inline The assigned timeslot masks are 64bit values. In case of 64 timeslots the code uses (1 << 64) which is undefined on a 64bit value. On the PowerPC architecture, this lead to an incorrect result as (1 << 64) produces the same result as (1 << 0). Fix the masks values taking care of the 64 timeslots case. Signed-off-by: Herve Codina --- drivers/soc/fsl/qe/qmc.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c index cfa7207353e0..b3c292c9a14e 100644 --- a/drivers/soc/fsl/qe/qmc.c +++ b/drivers/soc/fsl/qe/qmc.c @@ -754,6 +754,11 @@ static int qmc_check_chans(struct qmc *qmc) if (ret) return ret; + if ((info.nb_tx_ts > 64) || (info.nb_rx_ts > 64)) { + dev_err(qmc->dev, "Number of TSA Tx/Rx TS assigned not supported\n"); + return -EINVAL; + } + /* * If more than 32 TS are assigned to this serial, one common table is * used for Tx and Rx and so masks must be equal for all channels. @@ -766,9 +771,8 @@ static int qmc_check_chans(struct qmc *qmc) is_one_table = true; } - - tx_ts_assigned_mask = (((u64)1) << info.nb_tx_ts) - 1; - rx_ts_assigned_mask = (((u64)1) << info.nb_rx_ts) - 1; + tx_ts_assigned_mask = info.nb_tx_ts == 64 ? U64_MAX : (((u64)1) << info.nb_tx_ts) - 1; + rx_ts_assigned_mask = info.nb_rx_ts == 64 ? U64_MAX : (((u64)1) << info.nb_rx_ts) - 1; list_for_each_entry(chan, &qmc->chan_head, list) { if (chan->tx_ts_mask > tx_ts_assigned_mask) {