From patchwork Mon Mar 12 16:40:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 131390 Delivered-To: patch@linaro.org Received: by 10.80.194.209 with SMTP id u17csp4408615edf; Mon, 12 Mar 2018 09:40:28 -0700 (PDT) X-Google-Smtp-Source: AG47ELuXEtyqRHYAML50NtnYRgzgBYWoQKyHXuy5YbOvMt6kdrn56PXYINC9HbmYQqKZAJ+cqLeZ X-Received: by 10.223.187.199 with SMTP id z7mr7232599wrg.58.1520872828179; Mon, 12 Mar 2018 09:40:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1520872828; cv=none; d=google.com; s=arc-20160816; b=XIGQeebSmm7gkL7b7yrZ64mG+x39Ymw/6ac3d2yOqVnRTaufefLpG7O5h+QuomtH9M 1nFrLpNDdX2LYY+7Bf400E4n+71gX0I5h2bBEz+UpZj5L4ogTQQvSRt7L/ixitFiaw3V ClisX8FNLemUwX11S20NBpNat9i4TLoqXxRB0QngIzlZpAjhGEK4blkiCG+p0zyN/5Go 8ST2uopC/3vVsenF1yyKM3DrYUnLS64uD4RbBp1J1n3SQ8keBfvJ/AxONfy/ISlhYGva JReK5WIHmYS1H6I8k0iPgiR1oBfZ+7V+kj8acZ1eeQcrw+EHA996HO1rouYzTFnG6raq JgoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:date:message-id:in-reply-to:to:from :dkim-signature:delivered-to:arc-authentication-results; bh=oMPGBWGjKFOAnY6XNjbtedvovG4E0lt6Rk8KyVJyCVU=; b=IcTLyq69H0sLob4P8wuM+G3u08y+VMDS6kVh1mesnYnz1gHJph/vAY48pE/UCKd8FZ BYuTdLqC3YCflpiyM1NHr7DgNEE+W+6F4MdIF7vhILRF+mZsPOdBMLobpRbHEl5he1Bq LnPcq4PS7njIRTqfwand7O/mG8PYi8SlXtebYf7zSdrbpALyq58fuDdf2V7sP3mzM8WF b1jKW17IHx/lc+Uh24qCtzLPAQ7P18CoX9nY9J3ytThZ2HC6P6gPIYXSa+pGvb0TpVLA BmW4OVoECqaIA2XmzXs40TkyjQlUx2Moy3YsdD03DDKI3N08rYfzWeiyT6JRLm2NU4PB 5QqA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@sirena.org.uk header.s=20170815-heliosphere header.b=jC7UF9Qm; spf=pass (google.com: domain of alsa-devel-bounces@alsa-project.org designates 77.48.224.243 as permitted sender) smtp.mailfrom=alsa-devel-bounces@alsa-project.org Return-Path: Received: from alsa0.perex.cz (alsa0.perex.cz. [77.48.224.243]) by mx.google.com with ESMTP id l17si5604483wrg.110.2018.03.12.09.40.27; Mon, 12 Mar 2018 09:40:28 -0700 (PDT) Received-SPF: pass (google.com: domain of alsa-devel-bounces@alsa-project.org designates 77.48.224.243 as permitted sender) client-ip=77.48.224.243; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@sirena.org.uk header.s=20170815-heliosphere header.b=jC7UF9Qm; spf=pass (google.com: domain of alsa-devel-bounces@alsa-project.org designates 77.48.224.243 as permitted sender) smtp.mailfrom=alsa-devel-bounces@alsa-project.org Received: from alsa0.perex.cz (localhost [127.0.0.1]) by alsa0.perex.cz (Postfix) with ESMTP id D95E52674D1; Mon, 12 Mar 2018 17:40:17 +0100 (CET) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id CF90A2674D6; Mon, 12 Mar 2018 17:40:15 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail1.perex.cz X-Spam-Level: X-Spam-Status: No, score=0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, SPF_PASS, T_RP_MATCHES_RCVD autolearn=disabled version=3.4.0 Received: from heliosphere.sirena.org.uk (heliosphere.sirena.org.uk [172.104.155.198]) by alsa0.perex.cz (Postfix) with ESMTP id 9C79526743E for ; Mon, 12 Mar 2018 17:40:13 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sirena.org.uk; s=20170815-heliosphere; h=Date:Message-Id:In-Reply-To: Subject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:References: List-Id:List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner: List-Archive; bh=vtxuVZ27euUp+9nHQMHHo/3NbNcGKb/AIHqZbWFI9Zc=; b=jC7UF9QmiSPO 2kCNE17c3ZgRag5EIio7ZUYoXB1rPqS/PyD13vzMfUvHNNR+LeDzbhic+SSGY/eSzLjYITy5TIg8Y FGvdYKYlh/2NERf1OzcAMEDu5WlfEkc4hNP8juDsPGNeWFvZMIAqEtgGRVPwX5jkkvLcWGpehKrjh evylk=; Received: from [65.153.83.185] (helo=finisterre.ee.mobilebroadband) by heliosphere.sirena.org.uk with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1evQUc-00067O-4h; Mon, 12 Mar 2018 16:40:10 +0000 Received: by finisterre.ee.mobilebroadband (Postfix, from userid 1000) id 38843440079; Mon, 12 Mar 2018 16:40:08 +0000 (GMT) From: Mark Brown To: Bard Liao In-Reply-To: <1520855409-28862-3-git-send-email-bardliao@realtek.com> Message-Id: <20180312164008.38843440079@finisterre.ee.mobilebroadband> Date: Mon, 12 Mar 2018 16:40:08 +0000 (GMT) Cc: oder_chiou@realtek.com, jack.yu@realtek.com, alsa-devel@alsa-project.org, lars@metafoo.de, lgirdwood@gmail.com, broonie@kernel.org, shumingf@realtek.com, zhongan@pinecone.net, flove@realtek.com Subject: [alsa-devel] Applied "ASoC: rt5659: Separate adc 1/2 clock control" to the asoc tree X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org The patch ASoC: rt5659: Separate adc 1/2 clock control has been applied to the asoc tree at https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark >From ce571b80e2b2411d5cdfa78888a6865f918621c6 Mon Sep 17 00:00:00 2001 From: Bard Liao Date: Mon, 12 Mar 2018 19:50:09 +0800 Subject: [PATCH] ASoC: rt5659: Separate adc 1/2 clock control The control bits of ADC 1 and 2 clock are different. We have to separate it. Signed-off-by: Zhong An Signed-off-by: Bard Liao Signed-off-by: Mark Brown --- sound/soc/codecs/rt5659.c | 38 ++++++++++++++++++++++++++++++++------ sound/soc/codecs/rt5659.h | 12 ++++++++---- 2 files changed, 40 insertions(+), 10 deletions(-) -- 2.16.2 _______________________________________________ Alsa-devel mailing list Alsa-devel@alsa-project.org http://mailman.alsa-project.org/mailman/listinfo/alsa-devel diff --git a/sound/soc/codecs/rt5659.c b/sound/soc/codecs/rt5659.c index a81e248dfdcd..1c1a521c73cb 100644 --- a/sound/soc/codecs/rt5659.c +++ b/sound/soc/codecs/rt5659.c @@ -1622,7 +1622,7 @@ static int set_dmic_clk(struct snd_soc_dapm_widget *w, return idx; } -static int set_adc_clk(struct snd_soc_dapm_widget *w, +static int set_adc1_clk(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); @@ -1630,13 +1630,39 @@ static int set_adc_clk(struct snd_soc_dapm_widget *w, switch (event) { case SND_SOC_DAPM_POST_PMU: snd_soc_component_update_bits(component, RT5659_CHOP_ADC, - RT5659_CKXEN_ADCC_MASK | RT5659_CKGEN_ADCC_MASK, - RT5659_CKXEN_ADCC_MASK | RT5659_CKGEN_ADCC_MASK); + RT5659_CKXEN_ADC1_MASK | RT5659_CKGEN_ADC1_MASK, + RT5659_CKXEN_ADC1_MASK | RT5659_CKGEN_ADC1_MASK); break; case SND_SOC_DAPM_PRE_PMD: snd_soc_component_update_bits(component, RT5659_CHOP_ADC, - RT5659_CKXEN_ADCC_MASK | RT5659_CKGEN_ADCC_MASK, 0); + RT5659_CKXEN_ADC1_MASK | RT5659_CKGEN_ADC1_MASK, 0); + break; + + default: + return 0; + } + + return 0; + +} + +static int set_adc2_clk(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + snd_soc_component_update_bits(component, RT5659_CHOP_ADC, + RT5659_CKXEN_ADC2_MASK | RT5659_CKGEN_ADC2_MASK, + RT5659_CKXEN_ADC2_MASK | RT5659_CKGEN_ADC2_MASK); + break; + + case SND_SOC_DAPM_PRE_PMD: + snd_soc_component_update_bits(component, RT5659_CHOP_ADC, + RT5659_CKXEN_ADC2_MASK | RT5659_CKGEN_ADC2_MASK, 0); break; default: @@ -2559,9 +2585,9 @@ static const struct snd_soc_dapm_widget rt5659_dapm_widgets[] = { RT5659_PWR_ADC_L2_BIT, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("ADC2 R Power", RT5659_PWR_DIG_1, RT5659_PWR_ADC_R2_BIT, 0, NULL, 0), - SND_SOC_DAPM_SUPPLY("ADC1 clock", SND_SOC_NOPM, 0, 0, set_adc_clk, + SND_SOC_DAPM_SUPPLY("ADC1 clock", SND_SOC_NOPM, 0, 0, set_adc1_clk, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), - SND_SOC_DAPM_SUPPLY("ADC2 clock", SND_SOC_NOPM, 0, 0, set_adc_clk, + SND_SOC_DAPM_SUPPLY("ADC2 clock", SND_SOC_NOPM, 0, 0, set_adc2_clk, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), /* ADC Mux */ diff --git a/sound/soc/codecs/rt5659.h b/sound/soc/codecs/rt5659.h index 3b51c8a46e6e..8b576d768744 100644 --- a/sound/soc/codecs/rt5659.h +++ b/sound/soc/codecs/rt5659.h @@ -1743,10 +1743,14 @@ #define RT5659_CKGEN_DAC2_SFT 4 /* Chopper and Clock control for ADC (0x013b)*/ -#define RT5659_CKXEN_ADCC_MASK (0x1 << 13) -#define RT5659_CKXEN_ADCC_SFT 13 -#define RT5659_CKGEN_ADCC_MASK (0x1 << 12) -#define RT5659_CKGEN_ADCC_SFT 12 +#define RT5659_CKXEN_ADC1_MASK (0x1 << 13) +#define RT5659_CKXEN_ADC1_SFT 13 +#define RT5659_CKGEN_ADC1_MASK (0x1 << 12) +#define RT5659_CKGEN_ADC1_SFT 12 +#define RT5659_CKXEN_ADC2_MASK (0x1 << 5) +#define RT5659_CKXEN_ADC2_SFT 5 +#define RT5659_CKGEN_ADC2_MASK (0x1 << 4) +#define RT5659_CKGEN_ADC2_SFT 4 /* Test Mode Control 1 (0x0145) */ #define RT5659_AD2DA_LB_MASK (0x1 << 9)