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[86.26.103.58]) by smtp.gmail.com with ESMTPSA id a18sm50014661wrg.13.2022.02.22.03.59.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Feb 2022 03:59:57 -0800 (PST) From: Srinivas Kandagatla To: broonie@kernel.org Subject: [PATCH 10/16] ASoC: codecs: rx-macro: fix tlv min max range Date: Tue, 22 Feb 2022 11:59:27 +0000 Message-Id: <20220222115933.9114-11-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20220222115933.9114-1-srinivas.kandagatla@linaro.org> References: <20220222115933.9114-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Cc: alsa-devel@alsa-project.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, pierre-louis.bossart@linux.intel.com, tiwai@suse.com, Srinivas Kandagatla , quic_srivasam@quicinc.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" on Qualcomm codecs gain tlv control specifies min max range as both negative to positive numbers like SOC_SINGLE_S8_TLV("... Volume", .., -84, 40, gain) However with recent boundary checks added in commit 817f7c9335ec0 ("ASoC: ops: Reject out of bounds values in snd_soc_put_volsw()) setting a value above 40 gain will fail. So fix this min max range correctly to SOC_SINGLE_S8_TLV("... Volume", .., 0, 124, gain) so that users can now set gain correctly Fixes: af3d54b99764 ("ASoC: codecs: lpass-rx-macro: add support for lpass rx macro") Signed-off-by: Srinivas Kandagatla --- sound/soc/codecs/lpass-rx-macro.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/sound/soc/codecs/lpass-rx-macro.c b/sound/soc/codecs/lpass-rx-macro.c index 058d8634ce40..d31d4d45ba01 100644 --- a/sound/soc/codecs/lpass-rx-macro.c +++ b/sound/soc/codecs/lpass-rx-macro.c @@ -2800,17 +2800,17 @@ static int rx_macro_iir_filter_info(struct snd_kcontrol *kcontrol, static const struct snd_kcontrol_new rx_macro_snd_controls[] = { SOC_SINGLE_S8_TLV("RX_RX0 Digital Volume", CDC_RX_RX0_RX_VOL_CTL, - -84, 40, digital_gain), + 0, 124, digital_gain), SOC_SINGLE_S8_TLV("RX_RX1 Digital Volume", CDC_RX_RX1_RX_VOL_CTL, - -84, 40, digital_gain), + 0, 124, digital_gain), SOC_SINGLE_S8_TLV("RX_RX2 Digital Volume", CDC_RX_RX2_RX_VOL_CTL, - -84, 40, digital_gain), + 0, 124, digital_gain), SOC_SINGLE_S8_TLV("RX_RX0 Mix Digital Volume", CDC_RX_RX0_RX_VOL_MIX_CTL, - -84, 40, digital_gain), + 0, 124, digital_gain), SOC_SINGLE_S8_TLV("RX_RX1 Mix Digital Volume", CDC_RX_RX1_RX_VOL_MIX_CTL, - -84, 40, digital_gain), + 0, 124, digital_gain), SOC_SINGLE_S8_TLV("RX_RX2 Mix Digital Volume", CDC_RX_RX2_RX_VOL_MIX_CTL, - -84, 40, digital_gain), + 0, 124, digital_gain), SOC_SINGLE_EXT("RX_COMP1 Switch", SND_SOC_NOPM, RX_MACRO_COMP1, 1, 0, rx_macro_get_compander, rx_macro_set_compander), @@ -2834,28 +2834,28 @@ static const struct snd_kcontrol_new rx_macro_snd_controls[] = { rx_macro_aux_hpf_mode_put), SOC_SINGLE_S8_TLV("IIR0 INP0 Volume", - CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40, + CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 0, 124, digital_gain), SOC_SINGLE_S8_TLV("IIR0 INP1 Volume", - CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40, + CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, 0, 124, digital_gain), SOC_SINGLE_S8_TLV("IIR0 INP2 Volume", - CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40, + CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, 0, 124, digital_gain), SOC_SINGLE_S8_TLV("IIR0 INP3 Volume", - CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40, + CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, 0, 124, digital_gain), SOC_SINGLE_S8_TLV("IIR1 INP0 Volume", - CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40, + CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, 0, 124, digital_gain), SOC_SINGLE_S8_TLV("IIR1 INP1 Volume", - CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40, + CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, 0, 124, digital_gain), SOC_SINGLE_S8_TLV("IIR1 INP2 Volume", - CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40, + CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, 0, 124, digital_gain), SOC_SINGLE_S8_TLV("IIR1 INP3 Volume", - CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40, + CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, 0, 124, digital_gain), SOC_SINGLE("IIR1 Band1 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,