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[92.40.169.68]) by smtp.gmail.com with ESMTPSA id c5-20020adffb45000000b0021b91d1ddbfsm2917554wrs.21.2022.06.20.13.06.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:19 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 03/49] regmap-irq: Remove an unnecessary restriction on type_in_mask Date: Mon, 20 Jun 2022 21:05:58 +0100 Message-Id: <20220620200644.1961936-4-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:17 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Check types_supported instead of checking type_rising/falling_val when using type_in_mask interrupts. This makes the intent clearer and allows a type_in_mask irq to support level or edge triggers, rather than only edge triggers. Update the comment to reflect the new behavior. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index a6db605707b0..59cfd4000e63 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -253,22 +253,19 @@ static void regmap_irq_enable(struct irq_data *data) struct regmap *map = d->map; const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); unsigned int reg = irq_data->reg_offset / map->reg_stride; - unsigned int mask, type; - - type = irq_data->type.type_falling_val | irq_data->type.type_rising_val; + unsigned int mask; /* * The type_in_mask flag means that the underlying hardware uses - * separate mask bits for rising and falling edge interrupts, but - * we want to make them into a single virtual interrupt with - * configurable edge. + * separate mask bits for each interrupt trigger type, but we want + * to have a single logical interrupt with a configurable type. * - * If the interrupt we're enabling defines the falling or rising - * masks then instead of using the regular mask bits for this - * interrupt, use the value previously written to the type buffer - * at the corresponding offset in regmap_irq_set_type(). + * If the interrupt we're enabling defines any supported types + * then instead of using the regular mask bits for this interrupt, + * use the value previously written to the type buffer at the + * corresponding offset in regmap_irq_set_type(). */ - if (d->chip->type_in_mask && type) + if (d->chip->type_in_mask && irq_data->type.types_supported) mask = d->type_buf[reg] & irq_data->mask; else mask = irq_data->mask;