From patchwork Mon Aug 22 18:59:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Pierre-Louis Bossart X-Patchwork-Id: 599236 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A4A36C28D13 for ; Mon, 22 Aug 2022 19:01:41 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id D99B71682; Mon, 22 Aug 2022 21:00:49 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz D99B71682 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1661194899; bh=kaAAmkx7iP5OALaS8lXEWqptDm/29HsZXGDfo/Av3Ug=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=UrXa4/UP5jQ+3EjCFkUdWcbZU5y9elTd/7+4gaEmT+VGOcs05/FhKK96jV5nR/tEE jmSTvgt3LHXtKXTc8FDiFXrx3Jr39nzUedAmRFsUT2IdRtHbmTcXT0A5gCOivHiaQ+ HDcf+jWXaNPnhAL/ZSrUS7TeKpykDb4dIOd45giU= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 5CCD9F80548; Mon, 22 Aug 2022 20:59:50 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 721C3F80549; Mon, 22 Aug 2022 20:59:49 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 1334AF80152 for ; Mon, 22 Aug 2022 20:59:45 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 1334AF80152 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="BY9lNrGI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1661194787; x=1692730787; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kaAAmkx7iP5OALaS8lXEWqptDm/29HsZXGDfo/Av3Ug=; b=BY9lNrGIcNVXjO86Y059T9u43+rRUDYhcnLqQ8+K3IUqNaZq3a/j+kI7 dGlXcNy3G4XP9yLKKSBs3Lg5w5732w5Bfg+xI1mHpx+fvKJH6FaYrwKxZ 33z+vKUfPW6oiweRWillqG1MoIBQKy1UdGYzuU5OamOh3oDZGWMfiQxTv t0+VdWelYqD2/Uh/7aaEGOr+YKfts2iy4XitVRnaJ67ZYY4gxJTNs71jQ 0ZfxuX1MVHh2nRcxzB1c9GV9R1qZ0CoBhoK0BtOjMiS4SvzR26OKGRXwy VcNN5WuRqG9NKYMeG0LNSTEkkAHRhw8qGiX5/w7e5e0b07aPTaXCA0zdv g==; X-IronPort-AV: E=McAfee;i="6500,9779,10447"; a="379786519" X-IronPort-AV: E=Sophos;i="5.93,255,1654585200"; d="scan'208";a="379786519" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2022 11:59:44 -0700 X-IronPort-AV: E=Sophos;i="5.93,255,1654585200"; d="scan'208";a="669676593" Received: from apascali-mobl2.ger.corp.intel.com (HELO pbossart-mobl3.home) ([10.252.42.21]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2022 11:59:42 -0700 From: Pierre-Louis Bossart To: alsa-devel@alsa-project.org Subject: [PATCH 4/4] ASoC: SOF: Intel: hda: refine SSP count support Date: Mon, 22 Aug 2022 20:59:11 +0200 Message-Id: <20220822185911.170440-5-pierre-louis.bossart@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822185911.170440-1-pierre-louis.bossart@linux.intel.com> References: <20220822185911.170440-1-pierre-louis.bossart@linux.intel.com> MIME-Version: 1.0 Cc: Cezary Rojewski , tiwai@suse.de, Bard Liao , Pierre-Louis Bossart , broonie@kernel.org, =?utf-8?q?P=C3=A9ter_Ujfalusi?= X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" The SSP count is incorrect for TGL and MTL devices, the SSP count is limited to 3 (I2SPC parameter in the Integration HAS). Signed-off-by: Pierre-Louis Bossart Reviewed-by: Bard Liao Reviewed-by: Péter Ujfalusi --- sound/soc/sof/intel/hda.h | 2 ++ sound/soc/sof/intel/mtl.c | 2 +- sound/soc/sof/intel/tgl.c | 8 ++++---- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/sound/soc/sof/intel/hda.h b/sound/soc/sof/intel/hda.h index 5ef3e8775e364..34c5ebd9556c1 100644 --- a/sound/soc/sof/intel/hda.h +++ b/sound/soc/sof/intel/hda.h @@ -441,6 +441,8 @@ #define APL_SSP_COUNT 6 #define CNL_SSP_COUNT 3 #define ICL_SSP_COUNT 6 +#define TGL_SSP_COUNT 3 +#define MTL_SSP_COUNT 3 /* SSP Registers */ #define SSP_SSC1_OFFSET 0x4 diff --git a/sound/soc/sof/intel/mtl.c b/sound/soc/sof/intel/mtl.c index 96239ebb1eedb..27add99b7f947 100644 --- a/sound/soc/sof/intel/mtl.c +++ b/sound/soc/sof/intel/mtl.c @@ -782,7 +782,7 @@ const struct sof_intel_dsp_desc mtl_chip_info = { .ipc_ctl = MTL_DSP_REG_HFIPCXCTL, .rom_status_reg = MTL_DSP_ROM_STS, .rom_init_timeout = 300, - .ssp_count = ICL_SSP_COUNT, + .ssp_count = MTL_SSP_COUNT, .ssp_base_offset = CNL_SSP_BASE_OFFSET, .sdw_shim_base = SDW_SHIM_BASE_ACE, .sdw_alh_base = SDW_ALH_BASE_ACE, diff --git a/sound/soc/sof/intel/tgl.c b/sound/soc/sof/intel/tgl.c index 6dfb4786c7824..2119973716809 100644 --- a/sound/soc/sof/intel/tgl.c +++ b/sound/soc/sof/intel/tgl.c @@ -121,7 +121,7 @@ const struct sof_intel_dsp_desc tgl_chip_info = { .ipc_ctl = CNL_DSP_REG_HIPCCTL, .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, .rom_init_timeout = 300, - .ssp_count = ICL_SSP_COUNT, + .ssp_count = TGL_SSP_COUNT, .ssp_base_offset = CNL_SSP_BASE_OFFSET, .sdw_shim_base = SDW_SHIM_BASE, .sdw_alh_base = SDW_ALH_BASE, @@ -144,7 +144,7 @@ const struct sof_intel_dsp_desc tglh_chip_info = { .ipc_ctl = CNL_DSP_REG_HIPCCTL, .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, .rom_init_timeout = 300, - .ssp_count = ICL_SSP_COUNT, + .ssp_count = TGL_SSP_COUNT, .ssp_base_offset = CNL_SSP_BASE_OFFSET, .sdw_shim_base = SDW_SHIM_BASE, .sdw_alh_base = SDW_ALH_BASE, @@ -167,7 +167,7 @@ const struct sof_intel_dsp_desc ehl_chip_info = { .ipc_ctl = CNL_DSP_REG_HIPCCTL, .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, .rom_init_timeout = 300, - .ssp_count = ICL_SSP_COUNT, + .ssp_count = TGL_SSP_COUNT, .ssp_base_offset = CNL_SSP_BASE_OFFSET, .sdw_shim_base = SDW_SHIM_BASE, .sdw_alh_base = SDW_ALH_BASE, @@ -190,7 +190,7 @@ const struct sof_intel_dsp_desc adls_chip_info = { .ipc_ctl = CNL_DSP_REG_HIPCCTL, .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, .rom_init_timeout = 300, - .ssp_count = ICL_SSP_COUNT, + .ssp_count = TGL_SSP_COUNT, .ssp_base_offset = CNL_SSP_BASE_OFFSET, .sdw_shim_base = SDW_SHIM_BASE, .sdw_alh_base = SDW_ALH_BASE,