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Tue, 29 Aug 2023 10:17:44 -0700 (PDT) From: Alex Bee To: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , David Airlie , Daniel Vetter , Lee Jones , Liam Girdwood , Mark Brown , Michael Turquette , Stephen Boyd , Vinod Koul , Kishon Vijay Abraham I Cc: Elaine Zhang , Johan Jonker , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, alsa-devel@alsa-project.org, linux-clk@vger.kernel.org, linux-phy@lists.infradead.org, Alex Bee Subject: [PATCH 21/31] ARM: dts: rockchip: add power controller for RK312x Date: Tue, 29 Aug 2023 19:16:37 +0200 Message-ID: <20230829171647.187787-22-knaerzche@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829171647.187787-1-knaerzche@gmail.com> References: <20230829171647.187787-1-knaerzche@gmail.com> MIME-Version: 1.0 X-MailFrom: knaerzche@gmail.com X-Mailman-Rule-Hits: nonmember-moderation X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-alsa-devel.alsa-project.org-0; header-match-alsa-devel.alsa-project.org-1 Message-ID-Hash: QWHVZIUCC6KON3YUR4NWIGGBQVQ4PXL3 X-Message-ID-Hash: QWHVZIUCC6KON3YUR4NWIGGBQVQ4PXL3 X-Mailman-Approved-At: Tue, 29 Aug 2023 18:26:45 +0000 X-Mailman-Version: 3.3.8 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: Add the power controller node and the correspondending qos nodes for RK312x. Signed-off-by: Alex Bee --- arch/arm/boot/dts/rockchip/rk312x.dtsi | 82 ++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rk312x.dtsi b/arch/arm/boot/dts/rockchip/rk312x.dtsi index 93560c4cd16a..617306a9edf7 100644 --- a/arch/arm/boot/dts/rockchip/rk312x.dtsi +++ b/arch/arm/boot/dts/rockchip/rk312x.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include / { compatible = "rockchip,rk3128"; @@ -133,6 +134,87 @@ smp-sram@0 { pmu: syscon@100a0000 { compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; reg = <0x100a0000 0x1000>; + + power: power-controller { + compatible = "rockchip,rk3128-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3128_PD_VIO { + reg = ; + clocks = <&cru ACLK_RGA>, + <&cru ACLK_LCDC0>, + <&cru ACLK_IEP>, + <&cru ACLK_CIF>, + <&cru ACLK_VIO0>, + <&cru ACLK_VIO1>, + <&cru DCLK_VOP>, + <&cru DCLK_EBC>, + <&cru HCLK_RGA>, + <&cru HCLK_VIO>, + <&cru HCLK_EBC>, + <&cru HCLK_LCDC0>, + <&cru HCLK_IEP>, + <&cru HCLK_CIF>, + <&cru HCLK_VIO_H2P>, + <&cru PCLK_MIPI>, + <&cru SCLK_VOP>; + pm_qos = <&qos_rga>, + <&qos_iep>, + <&qos_lcdc>, + <&qos_vip>; + #power-domain-cells = <0>; + }; + + power-domain@RK3128_PD_VIDEO { + reg = ; + clocks = <&cru ACLK_VEPU>, + <&cru ACLK_VDPU>, + <&cru HCLK_VEPU>, + <&cru HCLK_VDPU>, + <&cru SCLK_HEVC_CORE>; + pm_qos = <&qos_vpu>; + #power-domain-cells = <0>; + }; + + power-domain@RK3128_PD_GPU { + reg = ; + clocks = <&cru ACLK_GPU>; + pm_qos = <&qos_gpu>; + #power-domain-cells = <0>; + }; + }; + }; + + qos_gpu: qos@1012d000 { + compatible = "rockchip,rk3128-qos", "syscon"; + reg = <0x1012d000 0x20>; + }; + + qos_vpu: qos@1012e000 { + compatible = "rockchip,rk3128-qos", "syscon"; + reg = <0x1012e000 0x20>; + }; + + qos_rga: qos@1012f000 { + compatible = "rockchip,rk3128-qos", "syscon"; + reg = <0x1012f000 0x20>; + }; + + qos_iep: qos@1012f100 { + compatible = "rockchip,rk3128-qos", "syscon"; + reg = <0x1012f100 0x20>; + }; + + qos_lcdc: qos@1012f180 { + compatible = "rockchip,rk3128-qos", "syscon"; + reg = <0x1012f180 0x20>; + }; + + qos_vip: qos@1012f200 { + compatible = "rockchip,rk3128-qos", "syscon"; + reg = <0x1012f200 0x20>; }; gic: interrupt-controller@10139000 {