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a="21291375" X-IronPort-AV: E=Sophos;i="6.07,232,1708416000"; d="scan'208";a="21291375" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2024 08:25:54 -0700 X-CSE-ConnectionGUID: 6ofE5vUVS8yURfdDkHnEFg== X-CSE-MsgGUID: Yan3E4FuRLSGJe3nTRbd+g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,232,1708416000"; d="scan'208";a="30259627" Received: from atarkhan-mobl2.amr.corp.intel.com (HELO pbossart-mobl6.intel.com) ([10.212.33.33]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2024 08:25:53 -0700 From: Pierre-Louis Bossart To: linux-sound@vger.kernel.org Cc: alsa-devel@alsa-project.org, tiwai@suse.de, broonie@kernel.org, Brent Lu , Bard Liao , Pierre-Louis Bossart Subject: [PATCH 23/23] ASoC: Intel: sof-rt5682: support bclk as PLL source on rt5682s Date: Fri, 26 Apr 2024 10:25:29 -0500 Message-Id: <20240426152529.38345-24-pierre-louis.bossart@linux.intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240426152529.38345-1-pierre-louis.bossart@linux.intel.com> References: <20240426152529.38345-1-pierre-louis.bossart@linux.intel.com> MIME-Version: 1.0 Message-ID-Hash: 6IVRQNL6OGTEEMR4Y2FFBZ7P46BLY2R5 X-Message-ID-Hash: 6IVRQNL6OGTEEMR4Y2FFBZ7P46BLY2R5 X-MailFrom: pierre-louis.bossart@linux.intel.com X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-alsa-devel.alsa-project.org-0; header-match-alsa-devel.alsa-project.org-1; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header X-Mailman-Version: 3.3.9 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: From: Brent Lu For rt5682s codec, we could use bclk as PLL source when the frequency is 3.072MHz but no 2.4MHz. Update the code to select correct pll_id and clk_id for 3.072MHz bclk. Reviewed-by: Bard Liao Signed-off-by: Brent Lu Signed-off-by: Pierre-Louis Bossart --- sound/soc/intel/boards/sof_rt5682.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/sound/soc/intel/boards/sof_rt5682.c b/sound/soc/intel/boards/sof_rt5682.c index c3b026868653..e3a2ec6b4c7c 100644 --- a/sound/soc/intel/boards/sof_rt5682.c +++ b/sound/soc/intel/boards/sof_rt5682.c @@ -355,18 +355,23 @@ static int sof_rt5682_hw_params(struct snd_pcm_substream *substream, clk_id = RT5682_SCLK_S_PLL1; break; case CODEC_RT5682S: - /* - * For MCLK = 24.576MHz and sample rate = 96KHz case, use PLL1 We don't test - * pll_out or params_rate() here since rt5682s PLL2 doesn't support 24.576MHz - * input, so we have no choice but to use PLL1. Besides, we will not use PLL at - * all if pll_in == pll_out. ex, MCLK = 24.576Mhz and sample rate = 48KHz - */ - if (pll_in == 24576000) { + /* check plla_table and pllb_table in rt5682s.c */ + switch (pll_in) { + case 3072000: + case 24576000: + /* + * For MCLK = 24.576MHz and sample rate = 96KHz case, use PLL1 We don't test + * pll_out or params_rate() here since rt5682s PLL2 doesn't support 24.576MHz + * input, so we have no choice but to use PLL1. Besides, we will not use PLL at + * all if pll_in == pll_out. ex, MCLK = 24.576Mhz and sample rate = 48KHz + */ pll_id = RT5682S_PLL1; clk_id = RT5682S_SCLK_S_PLL1; - } else { + break; + default: pll_id = RT5682S_PLL2; clk_id = RT5682S_SCLK_S_PLL2; + break; } break; default: