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Thu, 8 Aug 2024 11:58:22 -0500 From: Vijendar Mukunda To: CC: , , , , , , , , , , , , , , , , Vijendar Mukunda Subject: [PATCH RESEND 3/8] ASoC: SOF: amd: move iram-dram fence register programming sequence Date: Thu, 8 Aug 2024 22:27:48 +0530 Message-ID: <20240808165753.3414464-4-Vijendar.Mukunda@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240808165753.3414464-1-Vijendar.Mukunda@amd.com> References: <20240808165753.3414464-1-Vijendar.Mukunda@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB53:EE_|CH3PR12MB8548:EE_ X-MS-Office365-Filtering-Correlation-Id: a84714e4-e8a9-4620-2654-08dcb7cb52d3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|82310400026|7416014|376014|1800799024; X-Microsoft-Antispam-Message-Info: bKV+OQO2gn/MUaAu5SudUqR+DpNq7ZjyuhcJW4BEWdQvgJWf2vUBtPTYFm0TauKIFcTkfuvexQ9FPEk1rcs14NkQ6fKnC+Th71yUMAUQG93KE/5H/R61Wjvs691dTfc6ZZCO+6hCuGVNTBrowBShGgKKkL2QSJapPD2bgX1jO3JBaFvKnevNfIkx0CpJXprVGyLprVHn0PRKhL6mHJy/3ff87UgmYO1Hp89yBCsFlN2NR/q5bgBjPR0N977UWz6PIdr5CFd47dZbeZH5sl9miQUxo3WoOLa6Ql0HZTGlPdc7BRIaHHdK40gA2OjXKvsg6y8wJUxRkcEM3veU4a7ieqC7CojfBlV/6txeJbylG9CTNRbpljBpdL/gVwimpfX53J1LJrLwqoq5XJOUTVc+wdIG/Ia/LG4kDCvjFeZNHG4DlDubJWzfd9nErtfZOdjq5dh0ajR5Y8moE0GA9CgZxstfqtOKbogne6uNwJGsbvlTMEAN85hPCUOh5YPGkry5ywj71wWFLYGDUlZ9BIb/W9Do6doyYXWPw+AsKDaoA28KjG9GUCBQ0ZrhSU64D04fhnnyc9kKWCkhXBVjR3H6R5rr0UK8H3OL1pEdfwGRcOcQxnmx3vrPnE+dwhryCn9N3heKIm0+WK00mkXchPHB7xJDXfWimNNUS9nnHm/NQpsI3A3YC215kNRwoiROLKVNmcI/GydU99l9qVfIYtS6J9t0OTfdoX/FvETw3k2SffhmyZ/Rwdh/ulmBwKcUZ1AlTRj+9CqzqnZJzgKFdFidzMiU4htlKeMdwx2EoptAdn+yu4TKoTYKKByLS611Yny7ulfBr29qC4cRR94Ie6ZnC1SxiNQ2kQf8QhttjyGcwnWJawcGexORMW/b9Vx5zUmVgesLzBfendkop5msWvThGXjwDlXK6x8if8hxkKINknEzPg+fErBsjznFdCWFX28rkZTlZ5X6mOmO00iJPzZA5bXJ4KZC+TjzMTEHREc7OJKJKUIzm0yFKsGNkcrLeYMqEwilK9CJ9X6G/2UJkCkZ1a3rypUZIAJwxCgLrGJrsqQS0K4O+Cve6Yi/buMA3vmmrb7CE8qH7N7s1r6qlOdi3+Mfon03WNYLdEO5zEFBcYjsRSnKKOs+FEGTN0MabSHMgE22kMLHZxhqMLI/3K1j900b4+NxPz1M3wHp/2KusPgE0LRcXCOZ+ZElSqJuMsZ79RKcQECyT5PcrlMdm/ggkrpJMqxedenJX4EuQGKFCByT039jm4UwITLu5xrzEHTrF7FwjmFAsFJLrId3HN+i61BDFPPFhs/yC71kPRCSXkoq8E8hhqriysm1YUktvrdzgodz0PFGkHCcF70XYqJBu+nK9U558WBycRzyB+1AfkuSNM6gpWbf+keb10F8wLIEKID32PpQ/JsjLBjDvXQH0GzxZj3iHYVoGWcn5x7iFWzTf/+yPrIybjJlUa0rw1el X-Forefront-Antispam-Report: CIP:165.204.84.17; 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no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-alsa-devel.alsa-project.org-0; header-match-alsa-devel.alsa-project.org-1; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header X-Mailman-Version: 3.3.9 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: As per design, ACP iram-dram fence register sequence should be initiated before triggering SHA dma. This ensures that IRAM size will programmed correctly before initiaing SHA dma. Fixes: 094d11768f74 ("ASoC: SOF: amd: Skip IRAM/DRAM size modification for Steam Deck OLED") Signed-off-by: Vijendar Mukunda Reviewed-by: Ranjani Sridharan Reviewed-by: Pierre-Louis Bossart --- sound/soc/sof/amd/acp.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/sound/soc/sof/amd/acp.c b/sound/soc/sof/amd/acp.c index 9ce8b5ccb3d7..d0ba641ba28c 100644 --- a/sound/soc/sof/amd/acp.c +++ b/sound/soc/sof/amd/acp.c @@ -264,6 +264,17 @@ int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr, snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_STRT_ADDR, start_addr); snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_DESTINATION_ADDR, dest_addr); snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_MSG_LENGTH, image_length); + + /* psp_send_cmd only required for vangogh platform (rev - 5) */ + if (desc->rev == 5 && !(adata->quirks && adata->quirks->skip_iram_dram_size_mod)) { + /* Modify IRAM and DRAM size */ + ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | IRAM_DRAM_FENCE_2); + if (ret) + return ret; + ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | MBOX_ISREADY_FLAG); + if (ret) + return ret; + } snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RUN); ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_TRANSFER_BYTE_CNT, @@ -281,17 +292,6 @@ int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr, return ret; } - /* psp_send_cmd only required for vangogh platform (rev - 5) */ - if (desc->rev == 5 && !(adata->quirks && adata->quirks->skip_iram_dram_size_mod)) { - /* Modify IRAM and DRAM size */ - ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | IRAM_DRAM_FENCE_2); - if (ret) - return ret; - ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | MBOX_ISREADY_FLAG); - if (ret) - return ret; - } - ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DSP_FW_QUALIFIER, fw_qualifier, fw_qualifier & DSP_FW_RUN_ENABLE, ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US);