From patchwork Fri May 13 12:25:59 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 104901 Delivered-To: patch@linaro.org Received: by 10.140.92.199 with SMTP id b65csp239843qge; Fri, 13 May 2016 05:27:37 -0700 (PDT) X-Received: by 10.194.234.36 with SMTP id ub4mr15440627wjc.4.1463142457057; Fri, 13 May 2016 05:27:37 -0700 (PDT) Return-Path: Received: from alsa0.perex.cz (alsa0.perex.cz. [77.48.224.243]) by mx.google.com with ESMTP id q9si21954608wjl.108.2016.05.13.05.27.36; Fri, 13 May 2016 05:27:37 -0700 (PDT) Received-SPF: neutral (google.com: 77.48.224.243 is neither permitted nor denied by best guess record for domain of alsa-devel-bounces@alsa-project.org) client-ip=77.48.224.243; Authentication-Results: mx.google.com; spf=neutral (google.com: 77.48.224.243 is neither permitted nor denied by best guess record for domain of alsa-devel-bounces@alsa-project.org) smtp.mailfrom=alsa-devel-bounces@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id E98862669D0; Fri, 13 May 2016 14:27:35 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.2.4 (2008-01-01) on mail1.perex.cz X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=disabled version=3.2.4 Received: from alsa0.perex.cz (localhost [127.0.0.1]) by alsa0.perex.cz (Postfix) with ESMTP id E59362652B0; Fri, 13 May 2016 14:26:29 +0200 (CEST) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id EB4432606BB; Fri, 13 May 2016 14:26:26 +0200 (CEST) Received: from mezzanine.sirena.org.uk (mezzanine.sirena.org.uk [106.187.55.193]) by alsa0.perex.cz (Postfix) with ESMTP id 426F92605F1 for ; Fri, 13 May 2016 14:26:26 +0200 (CEST) Received: from 188.29.165.172.threembb.co.uk ([188.29.165.172] helo=finisterre) by mezzanine.sirena.org.uk with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.84_2) (envelope-from ) id 1b1CAS-0005h2-4t; Fri, 13 May 2016 12:26:10 +0000 Received: from broonie by finisterre with local (Exim 4.87) (envelope-from ) id 1b1CAJ-0007Le-5W; Fri, 13 May 2016 13:25:59 +0100 From: Mark Brown To: Arnaud Mouiche In-Reply-To: <1448550341-11765-6-git-send-email-arnaud.mouiche@invoxia.com> Message-Id: Date: Fri, 13 May 2016 13:25:59 +0100 X-SA-Exim-Connect-IP: 188.29.165.172 X-SA-Exim-Mail-From: broonie@sirena.org.uk X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:24:06 +0000) X-SA-Exim-Scanned: Yes (on mezzanine.sirena.org.uk) Cc: Fabio Estevam , alsa-devel@alsa-project.org, lgirdwood@gmail.com, Caleb Crome , Markus Pargmann , broonie@kernel.org, Roberto Fichera , "shawn.guo@linaro.org" Subject: [alsa-devel] Applied "ASoC: fsl_ssi: Fix channel slipping in Playback at startup" to the asoc tree X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org The patch ASoC: fsl_ssi: Fix channel slipping in Playback at startup has been applied to the asoc tree at git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark >From 61fcf10a0ee44763e0347b297a377137f8950772 Mon Sep 17 00:00:00 2001 From: Arnaud Mouiche Date: Tue, 3 May 2016 14:13:59 +0200 Subject: [PATCH] ASoC: fsl_ssi: Fix channel slipping in Playback at startup Previously, SCR.SSIEN and SCR.TE were enabled at once if no capture stream was also running. This may not give a chance for the DMA to write the first sample in TX FIFO before the streaming starts on the PCM bus, inserting void samples first. Those void samples are then responsible for slipping the channels. Signed-off-by: Arnaud Mouiche Reviewed-by: Fabio Estevam Tested-by: Caleb Crome Signed-off-by: Mark Brown --- sound/soc/fsl/fsl_ssi.c | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) -- 2.8.1 _______________________________________________ Alsa-devel mailing list Alsa-devel@alsa-project.org http://mailman.alsa-project.org/mailman/listinfo/alsa-devel diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c index 47ebb835f3f5..8944af542b4f 100644 --- a/sound/soc/fsl/fsl_ssi.c +++ b/sound/soc/fsl/fsl_ssi.c @@ -507,8 +507,40 @@ static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable, config_done: /* Enabling of subunits is done after configuration */ - if (enable) + if (enable) { + if (ssi_private->use_dma && (vals->scr & CCSR_SSI_SCR_TE)) { + /* + * Be sure the Tx FIFO is filled when TE is set. + * Otherwise, there are some chances to start the + * playback with some void samples inserted first, + * generating a channel slip. + * + * First, SSIEN must be set, to let the FIFO be filled. + * + * Notes: + * - Limit this fix to the DMA case until FIQ cases can + * be tested. + * - Limit the length of the busy loop to not lock the + * system too long, even if 1-2 loops are sufficient + * in general. + */ + int i; + int max_loop = 100; + regmap_update_bits(regs, CCSR_SSI_SCR, + CCSR_SSI_SCR_SSIEN, CCSR_SSI_SCR_SSIEN); + for (i = 0; i < max_loop; i++) { + u32 sfcsr; + regmap_read(regs, CCSR_SSI_SFCSR, &sfcsr); + if (CCSR_SSI_SFCSR_TFCNT0(sfcsr)) + break; + } + if (i == max_loop) { + dev_err(ssi_private->dev, + "Timeout waiting TX FIFO filling\n"); + } + } regmap_update_bits(regs, CCSR_SSI_SCR, vals->scr, vals->scr); + } }