diff --git a/gas/testsuite/gas/aarch64/fp-armv8_3.d b/gas/testsuite/gas/aarch64/fp-armv8_3.d
new file mode 100644
index 0000000..9be6fca
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp-armv8_3.d
@@ -0,0 +1,10 @@
+#objdump: -dr
+#as: -march=armv8.3-a
+
+.*:     file .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+   0:	1e7e0041 	fjcvtzs	w1, d2
+   4:	1e7e00e7 	fjcvtzs	w7, d7
diff --git a/gas/testsuite/gas/aarch64/fp-armv8_3.s b/gas/testsuite/gas/aarch64/fp-armv8_3.s
new file mode 100644
index 0000000..15db3d1
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp-armv8_3.s
@@ -0,0 +1,5 @@
+	/* ARMv8.3 Javascript conversion instruction.  */
+	.text
+
+	fjcvtzs w1, d2
+	fjcvtzs w7, d7
diff --git a/gas/testsuite/gas/aarch64/illegal-fjcvtzs.d b/gas/testsuite/gas/aarch64/illegal-fjcvtzs.d
new file mode 100644
index 0000000..000904b
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-fjcvtzs.d
@@ -0,0 +1,2 @@
+#as: -march=armv8.3-a -mno-verbose-error
+#error-output: illegal-fjcvtzs.l
diff --git a/gas/testsuite/gas/aarch64/illegal-fjcvtzs.l b/gas/testsuite/gas/aarch64/illegal-fjcvtzs.l
new file mode 100644
index 0000000..7a38ddc
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-fjcvtzs.l
@@ -0,0 +1,8 @@
+[^:]+: Assembler messages:
+[^:]+:8: Error: operand 1 must be an integer register -- `fjcvtzs d0,d1'
+[^:]+:9: Error: operand 1 must be an integer register -- `fjcvtzs s0,d1'
+[^:]+:10: Error: operand mismatch -- `fjcvtzs x0,d1'
+[^:]+:11: Error: operand mismatch -- `fjcvtzs w0,s1'
+[^:]+:12: Error: operand mismatch -- `fjcvtzs w0,h1'
+[^:]+:13: Error: operand mismatch -- `fjcvtzs w0,q1'
+[^:]+:14: Error: operand 2 must be a floating-point register -- `fjcvtzs w0,x1'
diff --git a/gas/testsuite/gas/aarch64/illegal-fjcvtzs.s b/gas/testsuite/gas/aarch64/illegal-fjcvtzs.s
new file mode 100644
index 0000000..74f6e3c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-fjcvtzs.s
@@ -0,0 +1,14 @@
+// Test illegal ARMv8.3 FJCVTZS instructions
+.text
+
+	// Good.
+	fjcvtzs w0, d1
+
+	// Bad.
+	fjcvtzs d0, d1
+	fjcvtzs s0, d1
+	fjcvtzs x0, d1
+	fjcvtzs w0, s1
+	fjcvtzs w0, h1
+	fjcvtzs w0, q1
+	fjcvtzs w0, x1
diff --git a/gas/testsuite/gas/aarch64/illegal-nofp-armv8_3.d b/gas/testsuite/gas/aarch64/illegal-nofp-armv8_3.d
new file mode 100644
index 0000000..89e0e89
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-nofp-armv8_3.d
@@ -0,0 +1,2 @@
+#as: -march=armv8.3-a+nofp -mno-verbose-error
+#error-output: illegal-nofp-armv8_3.l
diff --git a/gas/testsuite/gas/aarch64/illegal-nofp-armv8_3.l b/gas/testsuite/gas/aarch64/illegal-nofp-armv8_3.l
new file mode 100644
index 0000000..41d7fcc
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-nofp-armv8_3.l
@@ -0,0 +1,3 @@
+[^:]*: Assembler messages:
+[^:]+:4: Error: selected processor does not support `fneg s0,s1'
+[^:]+:6: Error: selected processor does not support `fjcvtzs w0,d1'
diff --git a/gas/testsuite/gas/aarch64/illegal-nofp-armv8_3.s b/gas/testsuite/gas/aarch64/illegal-nofp-armv8_3.s
new file mode 100644
index 0000000..549d89d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-nofp-armv8_3.s
@@ -0,0 +1,6 @@
+// Test -march=armv8.3-a+nofp to disable fp-dependent ARMv8.3 instructions.
+.text
+	neg w0, w1
+	fneg s0, s1
+	pacia x0, x1
+	fjcvtzs w0, d1
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 0aa8005..eb1274b 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -318,6 +318,12 @@
   QLF2 (X, S_H),			\
 }
 
+/* e.g. FJCVTZS <Wd>, <Dn>.  */
+#define QL_FP2INT_W_D			\
+{					\
+  QLF2 (W, S_D),			\
+}
+
 /* e.g. FMOV <Xd>, <Vn>.D[1].  */
 #define QL_XVD1			\
 {				\
@@ -1912,6 +1918,8 @@ static const aarch64_feature_set aarch64_feature_sve =
   AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0);
 static const aarch64_feature_set aarch64_feature_v8_3 =
   AARCH64_FEATURE (AARCH64_FEATURE_V8_3, 0);
+static const aarch64_feature_set aarch64_feature_fp_v8_3 =
+  AARCH64_FEATURE (AARCH64_FEATURE_V8_3 | AARCH64_FEATURE_FP, 0);
 
 #define CORE		&aarch64_feature_v8
 #define FP		&aarch64_feature_fp
@@ -1928,6 +1936,7 @@ static const aarch64_feature_set aarch64_feature_v8_3 =
 #define ARMV8_2		&aarch64_feature_v8_2
 #define SVE		&aarch64_feature_sve
 #define ARMV8_3		&aarch64_feature_v8_3
+#define FP_V8_3		&aarch64_feature_fp_v8_3
 
 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, NULL }
@@ -2789,6 +2798,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
   FF16_INSN ("fcvtzu",0x1ef90000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF),
   __FP_INSN ("fmov",  0x9eae0000, 0xfffffc00, float2int, 0, OP2 (Rd, VnD1), QL_XVD1, 0),
   __FP_INSN ("fmov",  0x9eaf0000, 0xfffffc00, float2int, 0, OP2 (VdD1, Rn), QL_VD1X, 0),
+  {"fjcvtzs", 0x1e7e0000, 0xfffffc00, float2int, 0, FP_V8_3, OP2 (Rd, Fn), QL_FP2INT_W_D, 0, 0, NULL },
   /* Floating-point conditional compare.  */
   __FP_INSN ("fccmp", 0x1e200400, 0xff200c10, floatccmp, 0, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP, F_FPTYPE),
   FF16_INSN ("fccmp", 0x1ee00400, 0xff200c10, floatccmp, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP_H, F_FPTYPE),

