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[2001:1868:205::9]) by mx.google.com with ESMTPS id 110si6801744qgv.13.2014.05.07.06.43.28 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 May 2014 06:43:28 -0700 (PDT) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Wi270-0004jD-Ll; Wed, 07 May 2014 13:42:18 +0000 Received: from mail-we0-f176.google.com ([74.125.82.176]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Wi26y-0004eE-GV for linux-arm-kernel@lists.infradead.org; Wed, 07 May 2014 13:42:17 +0000 Received: by mail-we0-f176.google.com with SMTP id q59so991901wes.21 for ; Wed, 07 May 2014 06:41:54 -0700 (PDT) X-Received: by 10.180.91.197 with SMTP id cg5mr26212893wib.35.1399470113969; Wed, 07 May 2014 06:41:53 -0700 (PDT) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id ez5sm26640807wjd.9.2014.05.07.06.41.52 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 May 2014 06:41:52 -0700 (PDT) From: Linus Walleij To: devicetree-discuss@lists.ozlabs.org, Grant Likely , Rob Herring Subject: [PATCH] ARM: dt: fix up PL011 device tree bindings Date: Wed, 7 May 2014 15:41:49 +0200 Message-Id: <1399470109-8021-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.9.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140507_064216_697310_C0B81BDB X-CRM114-Status: GOOD ( 16.13 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.3.2 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [74.125.82.176 listed in list.dnswl.org] Cc: Linus Walleij , Russell King , Arnd Bergmann , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: patch+caf_=patchwork-forward=linaro.org@linaro.org does not designate permitted sender hosts) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Make the map match the reality, the current binding text is nonsense: - The clock required for the clocking of the serial port must come first and is not optional (as the driver will otherwise proceed to grab and use the apb_pclk as uartclk), and the apb_pclk that clocks the logic must come second as the code will retrieve the first clock by index, whereas the PrimeCell but will explicitly look for "apb_pclk" so this can be specified later, as it is looked up by name. - The pin control state "default" is the only mandated state, the sleep state is entirely optional. We also add an example to avoid further confusion. Reported-by: Arnd Bergmann Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/serial/pl011.txt | 25 ++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/serial/pl011.txt b/Documentation/devicetree/bindings/serial/pl011.txt index 5d2e840ae65c..7a33d67c8349 100644 --- a/Documentation/devicetree/bindings/serial/pl011.txt +++ b/Documentation/devicetree/bindings/serial/pl011.txt @@ -6,12 +6,29 @@ Required properties: - interrupts: exactly one interrupt specifier Optional properties: -- pinctrl: When present, must have one state named "sleep" - and one state named "default" -- clocks: When present, must refer to exactly one clock named - "apb_pclk" +- pinctrl: When present, must have one state named "default", + and may contain a second name named "sleep". The former + state sets up pins for ordinary operation whereas + the latter state will put the associated pins to sleep + when the UART is unused +- clocks: When present, the first clock listed must be named + "uartclk" and clock the external serial line, and the + second clock listed must be named "amba_pclk" and clocks + the internal logic of the serial core - dmas: When present, may have one or two dma channels. The first one must be named "rx", the second one must be named "tx". See also bindings/arm/primecell.txt + +Example: + +uart@80120000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x80120000 0x1000>; + interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma 13 0 0x2>, <&dma 13 0 0x0>; + dma-names = "rx", "tx"; + clocks = <&foo_clk>, <&bar_clk>; + clock-names = "uartclk", "apb_pclk"; +};