From patchwork Sat Apr 24 10:36:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 426817 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2062464jao; Sat, 24 Apr 2021 03:39:09 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwNNA8QDta2m2AdTwBi/Nu2UPRLqICJBIdFJIK9SbBx/0C7TAs8/0WP5LLkoN4R3VDM/YlS X-Received: by 2002:a7b:c097:: with SMTP id r23mr8605414wmh.40.1619260749282; Sat, 24 Apr 2021 03:39:09 -0700 (PDT) Return-Path: Received: from mails.dpdk.org (mails.dpdk.org. [217.70.189.124]) by mx.google.com with ESMTP id q18si9307997wre.309.2021.04.24.03.39.09; Sat, 24 Apr 2021 03:39:09 -0700 (PDT) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 217.70.189.124 as permitted sender) client-ip=217.70.189.124; Authentication-Results: mx.google.com; dkim=fail header.i=@nxp.com header.s=selector2 header.b=je6KwFMd; arc=fail (signature failed); spf=pass (google.com: domain of dev-bounces@dpdk.org designates 217.70.189.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 772B04112E; Sat, 24 Apr 2021 12:38:48 +0200 (CEST) Received: from EUR01-DB5-obe.outbound.protection.outlook.com (mail-eopbgr150078.outbound.protection.outlook.com [40.107.15.78]) by mails.dpdk.org (Postfix) with ESMTP id 1203A41118 for ; Sat, 24 Apr 2021 12:38:45 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=DVJCK/jxgBbVzAXyhTmpRIzPpz9N/PKMdsOrgn1dsG78hLfphFODD0xVdhfDLNSTrBHvqd/aOaHCJ4cxTo9XLxo006vaaUPsVQVGP85oXgqaoVY3Z6xJztl2/ibgJilHAXUYC2fAluP46jBEc6zaKNgCHO1/YMKOplUTwPljVKhlBml6L89is8RQIr8Ds1PCwwdDjrqsaCfJjP+wnyJC+2Vw2dZsHe1/LyLV3eQx0cXeSyUCL3ECz5vWIuJYbpepss6M+jsA/kEhYte2i78CtwQLR1m+BHJMR9vW5IOpbbzdC5QK+w9Zi4y5QNAVq2BdQ1vHDt7KXZDWp9HM6w1XSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=fRd5w7qDs1EfApAXXC77gwBpmmaEm59hx6zaZBpW0Dw=; b=ktox89OTvtmCpbt/4uIYM9kV6zPINzDii8CPiT2kkGUjqlD/Lh7wueU14iUEN8vBJAm9jFW34WpDw7Eh4y1ShA7hEVfss5u6yTOnJ01wd2fDZieozdql/SzMe8C7YFNB/hIAtTGTCnLUdn9jibui4QszgnbwNS/sxiA9FV5o2WwvD16Taska2f4IidRHJciGUGzzglKOqcXp7uBLXE4E1PHV6cnvp5gkpf7mcGMDPRpBSifmSv6nYVoXvjHRQLPWZYo3xwbDn3ZIyCLwIM7JDuW8w5eiYQJi4yxpLhedn1imogCUfQVBOCuGv7XyC3eRiMsVij9bNOMt0TTn9/VArQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=fRd5w7qDs1EfApAXXC77gwBpmmaEm59hx6zaZBpW0Dw=; b=je6KwFMdnF0U3x8hQFqi9dOx1Z3GIIQZr0JmOlT7ctMG/7YcZKuC2L/jE54PzvdSlVlLzCrB37XprSQMJvY0nSE8BwJ6WcUFdbV6DgQ4poCMwoxfEDqCJjgyeH5k25w+0Gp56wvdIoJn1TOd8agYW7A/2zHcdyvfRG9zxBMvPyI= Authentication-Results: dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB4456.eurprd04.prod.outlook.com (2603:10a6:20b:22::25) by AM6PR0402MB3895.eurprd04.prod.outlook.com (2603:10a6:209:1a::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.25; Sat, 24 Apr 2021 10:38:44 +0000 Received: from AM6PR04MB4456.eurprd04.prod.outlook.com ([fe80::ad9e:a38e:e84e:bf55]) by AM6PR04MB4456.eurprd04.prod.outlook.com ([fe80::ad9e:a38e:e84e:bf55%6]) with mapi id 15.20.4065.023; Sat, 24 Apr 2021 10:38:44 +0000 From: Hemant Agrawal To: dev@dpdk.org, gakhil@marvell.com, nicolas.chautru@intel.com Cc: david.marchand@redhat.com, Hemant Agrawal , Nipun Gupta Date: Sat, 24 Apr 2021 16:06:58 +0530 Message-Id: <20210424103700.8098-7-hemant.agrawal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210424103700.8098-1-hemant.agrawal@nxp.com> References: <20210413051715.26430-2-hemant.agrawal@nxp.com> <20210424103700.8098-1-hemant.agrawal@nxp.com> X-Originating-IP: [92.120.0.67] X-ClientProxiedBy: HK2PR04CA0088.apcprd04.prod.outlook.com (2603:1096:202:15::32) To AM6PR04MB4456.eurprd04.prod.outlook.com (2603:10a6:20b:22::25) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from dpdk-xeon.ap.freescale.net (92.120.0.67) by HK2PR04CA0088.apcprd04.prod.outlook.com (2603:1096:202:15::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.21 via Frontend Transport; Sat, 24 Apr 2021 10:38:41 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 63110e5b-0abf-4b34-6bab-08d9070d2209 X-MS-TrafficTypeDiagnostic: AM6PR0402MB3895: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1060; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: mt7Gjay80YpiLMPuHCMRaTIwcq+w22Jo07wsziDSb0M4jukjMHXVtmn6DYsPyGXDThpinD/4moBNln8ToF7xwJnJKASqW8lajUF4Cmyhwz5O3UqGM1JYsuNlPPq9rFs7uLxCrq++bNhyLOQTELsIgzZkAmTEba9ttyJ8t9FsmIuxBJ4kTuxQcXQXB62ZIh55ul/4Kcp1Rr2x+hwB3cZuNyRePEB0ozS1ZXefYch+m0Dmp0RSS9bTgRY3UsGWB0eA0eKpuoEUwGx+WrYnmBFlRjgg4RKyAXKRLWKprP8XgiwOvEA8IK3q42wlawDJsN5OBRXITf1rRBr9jHR4ry9/B3aOCesy+OqZHfu2f/e3wx8qT51hBmAHZQK9j6CrsCC4pGg3Xx4K2d7esMIctP74srzwUUSbm420K/JfwBtl1IJkwsOcSYPsm9EMU9zKiNdKK5QcogngXqsvkK7DaZ7/GULAXg556oFP5D0bpgLa6Egd8XjFc/ZA1piAS1fl6+hKS3234ylveRW36j0wHRWJAZcF+YTXtBsZEQLrs5MZ1xthwQBfutWwPPiAfQBS/n5MPkTj+vv7BT9BgW3qoXc+LJhLDt1BkBQmqqI1vWlmxIMMLbTjhuLB5aCWgYTiiGSXAhiOE2PO3ZgpBDASwexnIU4mVdOz1RGqNIK/KmWe5ZQ= X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM6PR04MB4456.eurprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(39860400002)(396003)(136003)(376002)(366004)(346002)(8936002)(5660300002)(316002)(1076003)(54906003)(8676002)(6512007)(86362001)(478600001)(30864003)(38100700002)(2906002)(956004)(2616005)(38350700002)(36756003)(6666004)(186003)(83380400001)(26005)(4326008)(16526019)(6506007)(52116002)(6486002)(44832011)(66476007)(66556008)(66946007); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: R2yUhxHcUOkUn2Kf8yySk+zstGudU9eJoEUfjMWj4nSzvY8KfMs/vTDyk6ZQyp0T/fntXXDoDqB1CyakhrbVjQm5s+C+UcH4iJoUaCYXoeGkh61rh3Z/ipdZpfrs0VUD7UYda+kEbzmgR0Bf1MIcCRNzZ7wrFwtw0LypOejyips5fhe3LmQN8YSm8SaBLbcNOF5Lchy2UdyXX37OfJ2iKPrOITwGI4JA6A1VbscPOTCAXDRouDzyXi1OvCuwbu9Yg6lORCNsJOovl9gNcuheI4GXf0W+JMNP7X5etHC4Wr8aqTIaS0jBFvqdkvRnq0XkSAi9Qdog3N30ZZMDkNakOLhNire8uQkR14jZOZPzqJW3hSJBgEMRWIsPPJkAlCGnMZR/FsVHjFzOP2AeADkQ19yfDwGXVj/zLGrsWRsXJq1/w35Vz20X/5tNf0CP5nqv6S4JzoziyS3vhbgfJutCKjoxKPmyP3NYD3RBpwvfcyH8hPo4llRJ0pfKxu8mKm5HBLzuveY3qSr3hd9ksmY0o5QDJZa9G7m3EcrbUj3kJXCSd9qdkf1Uvbt8w4MiuClQfrI1LqdNC+G6LcOjtuR6627GdEk3xDknFfW5S2SI9JJPcpRh1wagqG9yqxLnBnVxWLAhGIGpngp34luBJ3l/CAQw2QXK8TI3G456g31T9hGAgEZEpEUACHUPk6DMgTgL5Xs+UVz3UcZmBFjOi7gFQtEaWPiZr+Wb0fhC0gq6tWDfJgPcRZhoojYbrIlh2qiwemLy3V/k+32rPFUgZEjTSvfzfsa5V0XTpEjqr1nX4RlPpUCZUquLsomK4N5hsJDGmuOIH/EMUOOMoBrFfK5gbwr35BKD/N/Ihg4VpjIQ9yQ6gHvWPbZDLGmR0KupESoQRyvqLYQxfP+xIdag+OkQzpsqvQLZaid0+JWPJR1U9f87qiTQbVASqhNzgvkEFyD7oCsFyOBQMpjX+OrgBui+c+2scfbBkTSxFTTlxtQpZY91cPszJJwXKFUmxg8UV6eyofiG5f4lUD2ONDUhFptnG2gJKEXCtP0lLI0l8pQz3YAus1ODPQPhyCIcp7vkCwm64eb4pMPI9BnX7KFV0zd017ePjhigXMBSH4g5iY7z4x7s7vgeh96R8hjJADfCIHs7nEZWQSQ4X+MyR0HHujONLvGbCnibKy5s4EDXg1JunlmCb6r5EBs+bBR2nehmKUx+fzFowSVkoRrHdyKXym5dkR1dcsXzbWiYx9uRtdxmZdCjAmNSuq9Y3iIS4IA1wMkU7x0i4+0ZsiHT1tOgGzLpB59U1muqD5mPW54qOiLvrB/+dbduzbpdM6pOtXWIbHej X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 63110e5b-0abf-4b34-6bab-08d9070d2209 X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4456.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Apr 2021 10:38:43.9786 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: tYxXyXURu5jMRX3tZD1KjHxoxkY3sszLXlM+YFfkBgSWtf2GGXemd28Lr57U1zj1MJhnYeEOIWBNDOoSeV17XA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR0402MB3895 Subject: [dpdk-dev] [PATCH v4 6/8] baseband/la12xx: add enqueue and dequeue support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for enqueue and dequeue the LDPC enc/dec from the modem device. Signed-off-by: Nipun Gupta Signed-off-by: Hemant Agrawal --- doc/guides/bbdevs/features/la12xx.ini | 14 + doc/guides/bbdevs/la12xx.rst | 46 +++ drivers/baseband/la12xx/bbdev_la12xx.c | 334 ++++++++++++++++++++- drivers/baseband/la12xx/bbdev_la12xx_ipc.h | 37 +++ 4 files changed, 425 insertions(+), 6 deletions(-) create mode 100644 doc/guides/bbdevs/features/la12xx.ini -- 2.17.1 diff --git a/doc/guides/bbdevs/features/la12xx.ini b/doc/guides/bbdevs/features/la12xx.ini new file mode 100644 index 0000000000..d184914b10 --- /dev/null +++ b/doc/guides/bbdevs/features/la12xx.ini @@ -0,0 +1,14 @@ +; +; Supported features of the 'la12xx' bbdev driver. +; +; Refer to default.ini for the full list of available PMD features. +; +[Features] +Turbo Decoder (4G) = N +Turbo Encoder (4G) = N +LDPC Decoder (5G) = Y +LDPC Encoder (5G) = Y +LLR/HARQ Compression = N +HW Accelerated = Y +BBDEV API = Y +Network Order Data = Y \ No newline at end of file diff --git a/doc/guides/bbdevs/la12xx.rst b/doc/guides/bbdevs/la12xx.rst index 3c9ac5c047..c39be0e51f 100644 --- a/doc/guides/bbdevs/la12xx.rst +++ b/doc/guides/bbdevs/la12xx.rst @@ -16,6 +16,8 @@ Features LA12xx PMD supports the following features: +- LDPC Encode in the DL +- LDPC Decode in the UL - Maximum of 8 UL queues - Maximum of 8 DL queues - PCIe Gen-3 x8 Interface @@ -79,3 +81,47 @@ For enabling logs, use the following EAL parameter: Using ``bb.la12xx`` as log matching criteria, all Baseband PMD logs can be enabled which are lower than logging ``level``. + +Test Application +---------------- + +BBDEV provides a test application, ``test-bbdev.py`` and range of test data for testing +the functionality of LA12xx for FEC encode and decode, depending on the device +capabilities. The test application is located under app->test-bbdev folder and has the +following options: + +.. code-block:: console + + "-p", "--testapp-path": specifies path to the bbdev test app. + "-e", "--eal-params" : EAL arguments which are passed to the test app. + "-t", "--timeout" : Timeout in seconds (default=300). + "-c", "--test-cases" : Defines test cases to run. Run all if not specified. + "-v", "--test-vector" : Test vector path (default=dpdk_path+/app/test-bbdev/test_vectors/bbdev_null.data). + "-n", "--num-ops" : Number of operations to process on device (default=32). + "-b", "--burst-size" : Operations enqueue/dequeue burst size (default=32). + "-s", "--snr" : SNR in dB used when generating LLRs for bler tests. + "-s", "--iter_max" : Number of iterations for LDPC decoder. + "-l", "--num-lcores" : Number of lcores to run (default=16). + "-i", "--init-device" : Initialise PF device with default values. + + +To execute the test application tool using simple decode or encode data, +type one of the following: + +.. code-block:: console + + ./test-bbdev.py -e="--vdev=baseband_la12xx,socket_id=0,max_nb_queues=8" -c validation -n 64 -b 1 -v ./ldpc_dec_default.data + ./test-bbdev.py -e="--vdev=baseband_la12xx,socket_id=0,max_nb_queues=8" -c validation -n 64 -b 1 -v ./ldpc_enc_default.data + +The test application ``test-bbdev.py``, supports the ability to configure the PF device with +a default set of values, if the "-i" or "- -init-device" option is included. The default values +are defined in test_bbdev_perf.c. + + +Test Vectors +~~~~~~~~~~~~ + +In addition to the simple LDPC decoder and LDPC encoder tests, bbdev also provides +a range of additional tests under the test_vectors folder, which may be useful. The results +of these tests will depend on the LA12xx FEC capabilities which may cause some +testcases to be skipped, but no failure should be reported. diff --git a/drivers/baseband/la12xx/bbdev_la12xx.c b/drivers/baseband/la12xx/bbdev_la12xx.c index 1fdeca279e..50e3284622 100644 --- a/drivers/baseband/la12xx/bbdev_la12xx.c +++ b/drivers/baseband/la12xx/bbdev_la12xx.c @@ -54,7 +54,8 @@ static const struct rte_bbdev_op_cap bbdev_capabilities[] = { .cap.ldpc_enc = { .capability_flags = RTE_BBDEV_LDPC_CRC_24A_ATTACH | - RTE_BBDEV_LDPC_CRC_24B_ATTACH, + RTE_BBDEV_LDPC_CRC_24B_ATTACH | + RTE_BBDEV_LDPC_ENC_NETWORK_ORDER, .num_buffers_src = RTE_BBDEV_LDPC_MAX_CODE_BLOCKS, .num_buffers_dst = @@ -68,7 +69,8 @@ static const struct rte_bbdev_op_cap bbdev_capabilities[] = { RTE_BBDEV_LDPC_CRC_TYPE_24A_CHECK | RTE_BBDEV_LDPC_LLR_COMPRESSION | RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK | - RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP, + RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP | + RTE_BBDEV_LDPC_DEC_NETWORK_ORDER, .num_buffers_src = RTE_BBDEV_LDPC_MAX_CODE_BLOCKS, .num_buffers_hard_out = @@ -121,6 +123,10 @@ la12xx_queue_release(struct rte_bbdev *dev, uint16_t q_id) ((uint64_t) ((unsigned long) (A) \ - ((uint64_t)ipc_priv->hugepg_start.host_vaddr))) +#define MODEM_P2V(A) \ + ((uint64_t) ((unsigned long) (A) \ + + (unsigned long)(ipc_priv->peb_start.host_vaddr))) + static int ipc_queue_configure(uint32_t channel_id, ipc_t instance, struct bbdev_la12xx_q_priv *q_priv) { @@ -335,6 +341,318 @@ static const struct rte_bbdev_ops pmd_ops = { .queue_release = la12xx_queue_release, .start = la12xx_start }; + +static inline int +is_bd_ring_full(uint32_t ci, uint32_t ci_flag, + uint32_t pi, uint32_t pi_flag) +{ + if (pi == ci) { + if (pi_flag != ci_flag) + return 1; /* Ring is Full */ + } + return 0; +} + +static inline int +prepare_ldpc_enc_op(struct rte_bbdev_enc_op *bbdev_enc_op, + struct bbdev_la12xx_q_priv *q_priv __rte_unused, + struct rte_bbdev_op_data *in_op_data __rte_unused, + struct rte_bbdev_op_data *out_op_data) +{ + struct rte_bbdev_op_ldpc_enc *ldpc_enc = &bbdev_enc_op->ldpc_enc; + uint32_t total_out_bits; + + total_out_bits = (ldpc_enc->tb_params.cab * + ldpc_enc->tb_params.ea) + (ldpc_enc->tb_params.c - + ldpc_enc->tb_params.cab) * ldpc_enc->tb_params.eb; + + ldpc_enc->output.length = (total_out_bits + 7)/8; + + rte_pktmbuf_append(out_op_data->data, ldpc_enc->output.length); + + return 0; +} + +static inline int +prepare_ldpc_dec_op(struct rte_bbdev_dec_op *bbdev_dec_op, + struct bbdev_ipc_dequeue_op *bbdev_ipc_op, + struct bbdev_la12xx_q_priv *q_priv __rte_unused, + struct rte_bbdev_op_data *out_op_data __rte_unused) +{ + struct rte_bbdev_op_ldpc_dec *ldpc_dec = &bbdev_dec_op->ldpc_dec; + uint32_t total_out_bits; + uint32_t num_code_blocks = 0; + uint16_t sys_cols; + + sys_cols = (ldpc_dec->basegraph == 1) ? 22 : 10; + if (ldpc_dec->tb_params.c == 1) { + total_out_bits = ((sys_cols * ldpc_dec->z_c) - + ldpc_dec->n_filler); + /* 5G-NR protocol uses 16 bit CRC when output packet + * size <= 3824 (bits). Otherwise 24 bit CRC is used. + * Adjust the output bits accordingly + */ + if (total_out_bits - 16 <= 3824) + total_out_bits -= 16; + else + total_out_bits -= 24; + ldpc_dec->hard_output.length = (total_out_bits / 8); + } else { + total_out_bits = (((sys_cols * ldpc_dec->z_c) - + ldpc_dec->n_filler - 24) * + ldpc_dec->tb_params.c); + ldpc_dec->hard_output.length = (total_out_bits / 8) - 3; + } + + num_code_blocks = ldpc_dec->tb_params.c; + + bbdev_ipc_op->num_code_blocks = rte_cpu_to_be_32(num_code_blocks); + + return 0; +} + +static int +enqueue_single_op(struct bbdev_la12xx_q_priv *q_priv, void *bbdev_op) +{ + struct bbdev_la12xx_private *priv = q_priv->bbdev_priv; + ipc_userspace_t *ipc_priv = priv->ipc_priv; + ipc_instance_t *ipc_instance = ipc_priv->instance; + struct bbdev_ipc_dequeue_op *bbdev_ipc_op; + struct rte_bbdev_op_ldpc_enc *ldpc_enc; + struct rte_bbdev_op_ldpc_dec *ldpc_dec; + uint32_t q_id = q_priv->q_id; + uint32_t ci, ci_flag, pi, pi_flag; + ipc_ch_t *ch = &(ipc_instance->ch_list[q_id]); + ipc_br_md_t *md = &(ch->md); + size_t virt; + char *huge_start_addr = + (char *)q_priv->bbdev_priv->ipc_priv->hugepg_start.host_vaddr; + struct rte_bbdev_op_data *in_op_data, *out_op_data; + char *data_ptr; + uint32_t l1_pcie_addr; + int ret; + + ci = IPC_GET_CI_INDEX(q_priv->host_ci); + ci_flag = IPC_GET_CI_FLAG(q_priv->host_ci); + + pi = IPC_GET_PI_INDEX(q_priv->host_pi); + pi_flag = IPC_GET_PI_FLAG(q_priv->host_pi); + + rte_bbdev_dp_log(DEBUG, "before bd_ring_full: pi: %u, ci: %u," + "pi_flag: %u, ci_flag: %u, ring size: %u", + pi, ci, pi_flag, ci_flag, q_priv->queue_size); + + if (is_bd_ring_full(ci, ci_flag, pi, pi_flag)) { + rte_bbdev_dp_log(DEBUG, "bd ring full for queue id: %d", q_id); + return IPC_CH_FULL; + } + + virt = MODEM_P2V(q_priv->host_params->bd_m_modem_ptr[pi]); + bbdev_ipc_op = (struct bbdev_ipc_dequeue_op *)virt; + q_priv->bbdev_op[pi] = bbdev_op; + + switch (q_priv->op_type) { + case RTE_BBDEV_OP_LDPC_ENC: + ldpc_enc = &(((struct rte_bbdev_enc_op *)bbdev_op)->ldpc_enc); + in_op_data = &ldpc_enc->input; + out_op_data = &ldpc_enc->output; + + ret = prepare_ldpc_enc_op(bbdev_op, q_priv, + in_op_data, out_op_data); + if (ret) { + rte_bbdev_log(ERR, "process_ldpc_enc_op fail, ret: %d", + ret); + return ret; + } + break; + + case RTE_BBDEV_OP_LDPC_DEC: + ldpc_dec = &(((struct rte_bbdev_dec_op *)bbdev_op)->ldpc_dec); + in_op_data = &ldpc_dec->input; + + out_op_data = &ldpc_dec->hard_output; + + ret = prepare_ldpc_dec_op(bbdev_op, bbdev_ipc_op, + q_priv, out_op_data); + if (ret) { + rte_bbdev_log(ERR, "process_ldpc_dec_op fail, ret: %d", + ret); + return ret; + } + break; + + default: + rte_bbdev_log(ERR, "unsupported bbdev_ipc op type"); + return -1; + } + + if (in_op_data->data) { + data_ptr = rte_pktmbuf_mtod(in_op_data->data, char *); + l1_pcie_addr = (uint32_t)GUL_USER_HUGE_PAGE_ADDR + + data_ptr - huge_start_addr; + bbdev_ipc_op->in_addr = l1_pcie_addr; + bbdev_ipc_op->in_len = in_op_data->length; + } + + if (out_op_data->data) { + data_ptr = rte_pktmbuf_mtod(out_op_data->data, char *); + l1_pcie_addr = (uint32_t)GUL_USER_HUGE_PAGE_ADDR + + data_ptr - huge_start_addr; + bbdev_ipc_op->out_addr = rte_cpu_to_be_32(l1_pcie_addr); + bbdev_ipc_op->out_len = rte_cpu_to_be_32(out_op_data->length); + } + + /* Move Producer Index forward */ + pi++; + /* Flip the PI flag, if wrapping */ + if (unlikely(q_priv->queue_size == pi)) { + pi = 0; + pi_flag = pi_flag ? 0 : 1; + } + + if (pi_flag) + IPC_SET_PI_FLAG(pi); + else + IPC_RESET_PI_FLAG(pi); + q_priv->host_pi = pi; + + /* Wait for Data Copy & pi_flag update to complete before updating pi */ + rte_mb(); + /* now update pi */ + md->pi = rte_cpu_to_be_32(pi); + + rte_bbdev_dp_log(DEBUG, "enter: pi: %u, ci: %u," + "pi_flag: %u, ci_flag: %u, ring size: %u", + pi, ci, pi_flag, ci_flag, q_priv->queue_size); + + return 0; +} + +/* Enqueue decode burst */ +static uint16_t +enqueue_dec_ops(struct rte_bbdev_queue_data *q_data, + struct rte_bbdev_dec_op **ops, uint16_t nb_ops) +{ + struct bbdev_la12xx_q_priv *q_priv = q_data->queue_private; + int nb_enqueued, ret; + + for (nb_enqueued = 0; nb_enqueued < nb_ops; nb_enqueued++) { + ret = enqueue_single_op(q_priv, ops[nb_enqueued]); + if (ret) + break; + } + + q_data->queue_stats.enqueue_err_count += nb_ops - nb_enqueued; + q_data->queue_stats.enqueued_count += nb_enqueued; + + return nb_enqueued; +} + +/* Enqueue encode burst */ +static uint16_t +enqueue_enc_ops(struct rte_bbdev_queue_data *q_data, + struct rte_bbdev_enc_op **ops, uint16_t nb_ops) +{ + struct bbdev_la12xx_q_priv *q_priv = q_data->queue_private; + int nb_enqueued, ret; + + for (nb_enqueued = 0; nb_enqueued < nb_ops; nb_enqueued++) { + ret = enqueue_single_op(q_priv, ops[nb_enqueued]); + if (ret) + break; + } + + q_data->queue_stats.enqueue_err_count += nb_ops - nb_enqueued; + q_data->queue_stats.enqueued_count += nb_enqueued; + + return nb_enqueued; +} + +/* Dequeue encode burst */ +static void * +dequeue_single_op(struct bbdev_la12xx_q_priv *q_priv, void *dst) +{ + void *op; + uint32_t ci, ci_flag; + uint32_t temp_ci; + + temp_ci = q_priv->host_params->ci; + if (temp_ci == q_priv->host_ci) + return NULL; + + ci = IPC_GET_CI_INDEX(q_priv->host_ci); + ci_flag = IPC_GET_CI_FLAG(q_priv->host_ci); + + rte_bbdev_dp_log(DEBUG, + "ci: %u, ci_flag: %u, ring size: %u", + ci, ci_flag, q_priv->queue_size); + + op = q_priv->bbdev_op[ci]; + + rte_memcpy(dst, q_priv->msg_ch_vaddr[ci], + sizeof(struct bbdev_ipc_enqueue_op)); + + /* Move Consumer Index forward */ + ci++; + /* Flip the CI flag, if wrapping */ + if (q_priv->queue_size == ci) { + ci = 0; + ci_flag = ci_flag ? 0 : 1; + } + if (ci_flag) + IPC_SET_CI_FLAG(ci); + else + IPC_RESET_CI_FLAG(ci); + + q_priv->host_ci = ci; + + rte_bbdev_dp_log(DEBUG, + "exit: ci: %u, ci_flag: %u, ring size: %u", + ci, ci_flag, q_priv->queue_size); + + return op; +} + +/* Dequeue decode burst */ +static uint16_t +dequeue_dec_ops(struct rte_bbdev_queue_data *q_data, + struct rte_bbdev_dec_op **ops, uint16_t nb_ops) +{ + struct bbdev_la12xx_q_priv *q_priv = q_data->queue_private; + struct bbdev_ipc_enqueue_op bbdev_ipc_op; + int nb_dequeued; + + for (nb_dequeued = 0; nb_dequeued < nb_ops; nb_dequeued++) { + ops[nb_dequeued] = dequeue_single_op(q_priv, &bbdev_ipc_op); + if (!ops[nb_dequeued]) + break; + ops[nb_dequeued]->status = bbdev_ipc_op.status; + } + q_data->queue_stats.dequeued_count += nb_dequeued; + + return nb_dequeued; +} + +/* Dequeue encode burst */ +static uint16_t +dequeue_enc_ops(struct rte_bbdev_queue_data *q_data, + struct rte_bbdev_enc_op **ops, uint16_t nb_ops) +{ + struct bbdev_la12xx_q_priv *q_priv = q_data->queue_private; + struct bbdev_ipc_enqueue_op bbdev_ipc_op; + int nb_enqueued; + + for (nb_enqueued = 0; nb_enqueued < nb_ops; nb_enqueued++) { + ops[nb_enqueued] = dequeue_single_op(q_priv, &bbdev_ipc_op); + if (!ops[nb_enqueued]) + break; + ops[nb_enqueued]->status = bbdev_ipc_op.status; + } + q_data->queue_stats.enqueued_count += nb_enqueued; + + return nb_enqueued; +} + static struct hugepage_info * get_hugepage_info(void) { @@ -708,10 +1026,14 @@ la12xx_bbdev_create(struct rte_vdev_device *vdev, bbdev->intr_handle = NULL; /* register rx/tx burst functions for data path */ - bbdev->dequeue_enc_ops = NULL; - bbdev->dequeue_dec_ops = NULL; - bbdev->enqueue_enc_ops = NULL; - bbdev->enqueue_dec_ops = NULL; + bbdev->dequeue_enc_ops = dequeue_enc_ops; + bbdev->dequeue_dec_ops = dequeue_dec_ops; + bbdev->enqueue_enc_ops = enqueue_enc_ops; + bbdev->enqueue_dec_ops = enqueue_dec_ops; + bbdev->dequeue_ldpc_enc_ops = dequeue_enc_ops; + bbdev->dequeue_ldpc_dec_ops = dequeue_dec_ops; + bbdev->enqueue_ldpc_enc_ops = enqueue_enc_ops; + bbdev->enqueue_ldpc_dec_ops = enqueue_dec_ops; return 0; } diff --git a/drivers/baseband/la12xx/bbdev_la12xx_ipc.h b/drivers/baseband/la12xx/bbdev_la12xx_ipc.h index 5f613fb087..b6a7f677d0 100644 --- a/drivers/baseband/la12xx/bbdev_la12xx_ipc.h +++ b/drivers/baseband/la12xx/bbdev_la12xx_ipc.h @@ -73,6 +73,25 @@ typedef struct { _IOWR(GUL_IPC_MAGIC, 5, struct ipc_msg *) #define IOCTL_GUL_IPC_CHANNEL_RAISE_INTERRUPT _IOW(GUL_IPC_MAGIC, 6, int *) +#define GUL_USER_HUGE_PAGE_OFFSET (0) +#define GUL_PCI1_ADDR_BASE (0x00000000ULL) + +#define GUL_USER_HUGE_PAGE_ADDR (GUL_PCI1_ADDR_BASE + GUL_USER_HUGE_PAGE_OFFSET) + +/* IPC PI/CI index & flag manipulation helpers */ +#define IPC_PI_CI_FLAG_MASK 0x80000000 /* (1<<31) */ +#define IPC_PI_CI_INDEX_MASK 0x7FFFFFFF /* ~(1<<31) */ + +#define IPC_SET_PI_FLAG(x) (x |= IPC_PI_CI_FLAG_MASK) +#define IPC_RESET_PI_FLAG(x) (x &= IPC_PI_CI_INDEX_MASK) +#define IPC_GET_PI_FLAG(x) (x >> 31) +#define IPC_GET_PI_INDEX(x) (x & IPC_PI_CI_INDEX_MASK) + +#define IPC_SET_CI_FLAG(x) (x |= IPC_PI_CI_FLAG_MASK) +#define IPC_RESET_CI_FLAG(x) (x &= IPC_PI_CI_INDEX_MASK) +#define IPC_GET_CI_FLAG(x) (x >> 31) +#define IPC_GET_CI_INDEX(x) (x & IPC_PI_CI_INDEX_MASK) + /** buffer ring common metadata */ typedef struct ipc_bd_ring_md { volatile uint32_t pi; /**< Producer index and flag (MSB) @@ -180,6 +199,24 @@ struct bbdev_ipc_enqueue_op { uint32_t rsvd; }; +/** Structure specifying dequeue operation (dequeue at LA1224) */ +struct bbdev_ipc_dequeue_op { + /** Input buffer memory address */ + uint32_t in_addr; + /** Input buffer memory length */ + uint32_t in_len; + /** Output buffer memory address */ + uint32_t out_addr; + /** Output buffer memory length */ + uint32_t out_len; + /* Number of code blocks. Only set when HARQ is used */ + uint32_t num_code_blocks; + /** Dequeue Operation flags */ + uint32_t op_flags; + /** Shared metadata between L1 and L2 */ + uint32_t shared_metadata; +}; + /* This shared memory would be on the host side which have copy of some * of the parameters which are also part of Shared BD ring. Read access * of these parameters from the host side would not be over PCI.