From patchwork Tue Nov 16 06:22:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 519175 Delivered-To: patch@linaro.org Received: by 2002:ac0:c605:0:0:0:0:0 with SMTP id p5csp6710086imj; Mon, 15 Nov 2021 22:23:17 -0800 (PST) X-Google-Smtp-Source: ABdhPJxSQloScmHiZk7gSBBFX15Kb8QEgJzvniW7qSyD2SQftmBX2ETITjjaLOdyAVA/BrEKSv6S X-Received: by 2002:a17:90a:e7c4:: with SMTP id kb4mr72981347pjb.237.1637043797716; Mon, 15 Nov 2021 22:23:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1637043797; cv=none; d=google.com; s=arc-20160816; b=z/D+8SZ5rqtqeZB/NtBSqghY1iP5JnP804+AeIxfCMNt7Z+Zc/kHi3LgvhkyGYYROW 6XejpWYCC2WcPLQxSA4GCKEPBpWcJfzxq0hTIb5fyXuz0arqaQjcV5YWIwO9vWuuK4/y Crwf/8R6hDm1jCpObTfrizN4YzOLJAMyi4PPO8X0VeB5SZK4jcBDaINSZp9fFq1rZ2CA sNQgXNw3auSqUNQ7EKBybEDhKKnOz37kFL7/INXvA9zcmwOXH72fUOERgRHGiHjkzSML BU4LvmPIH/QGY17/sYB5YokDyO25OQn1eif4b9VpGnMvJejkYUt50hfLy/JUWjRSkNki jZsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:message-id:date:subject:to:from:dkim-signature :delivered-to; bh=uYGLH3iU3KIYVpSPa3LmmBMOoPoGmEeG8pnh2H9gNDA=; b=eMOoBT+SbyPvT7jx25PH3AllbF0BXfQbzOKzJe1aBJcw/7Lp+zuWL2rshKokgJm/5W OQpp8rU4Cra1IfJuQtYmcnj/Xep0BBX1npN71pGT5RD3jzooy1nZp3kikWzBfXtnyO5u bDTVouWhan9diuzCxuLG7nDLD8csxr4WQVto8gffaO8czYc8rzyJwh4NiH5gpW2quAUH z0OK5JJ9N+xIp0ZmxEMTGR2lTsqwPlff54GtRHSAbxSS1NH5Tnfy4uhRd9w0lgeTg11S jlQ4Gy1PW6x0bzhD2+ePjV+/j5DNCYmTBe0GhlpsLlrOzk5p1TZzHq0OHRfhCp6paklp +qDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@kernel.org header.s=k20201202 header.b="k6s/QZ6K"; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [2610:10:20:722:a800:ff:fe36:1795]) by mx.google.com with ESMTPS id s1si2857711pjo.10.2021.11.15.22.23.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Nov 2021 22:23:17 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) client-ip=2610:10:20:722:a800:ff:fe36:1795; Authentication-Results: mx.google.com; dkim=fail header.i=@kernel.org header.s=k20201202 header.b="k6s/QZ6K"; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4843D6E8F1; Tue, 16 Nov 2021 06:23:14 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6C8466E064; Tue, 16 Nov 2021 06:23:13 +0000 (UTC) Received: by mail.kernel.org (Postfix) with ESMTPSA id AD9A861A79; Tue, 16 Nov 2021 06:23:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1637043793; bh=ENGSGQ1NXR7QbGxb7RhGtnDxvHhGd5nfvfBUhK6kcbE=; h=From:To:Cc:Subject:Date:From; b=k6s/QZ6K53gcAQFUjmhxoXZMBraqOkZGmAPSe2DhwLGu+lwlogxZ7HPbtvRxYL9mq cX0F22qWwvvqgy3GgCqS2743y65kZ85q3shs7KGeLl0yCFhWTUQV4ZAmcNPcm9CwbY 0S6Xlz6/kMv4CefqnTIpyZX1O/syRly0/uerjbQo9gEVmv94thnO3xCswwKog30x3I Dm2fruDrJyrxIhw/KDp/iHumsRfIHpPWRrdOxA++zsiBEmY2dDsLOQqq4u7mJp9XwZ J5BosVeL4Y6dHUPWY2HEk+EwfgNqrLQemVJbfB7kyvOW2pz2QaPH+UKDJb2IQ71alb xm9t3zmta+PlQ== From: Vinod Koul To: Rob Clark Subject: [PATCH v3 00/13] drm/msm: Add Display Stream Compression Support Date: Tue, 16 Nov 2021 11:52:43 +0530 Message-Id: <20211116062256.2417186-1-vkoul@kernel.org> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jonathan Marek , Jeffrey Hugo , David Airlie , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Abhinav Kumar , Bjorn Andersson , Vinod Koul , dri-devel@lists.freedesktop.org, Dmitry Baryshkov , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Display Stream Compression (DSC) compresses the display stream in host which is later decoded by panel. This series enables this for Qualcomm msm driver. This was tested on Google Pixel3 phone which use LGE SW43408 panel. The changes include DSC data and hardware block enabling for DPU1 then support in encoder. We also add support in DSI and introduce required topology changes. In order for panel to set the DSC parameters we add dsc in drm_panel and set it from the msm driver. We still have dsc as a globabl entity. I think while doing DP + DSC we should be able to update it, right now comprehending the requirements are bit difficult. Complete changes which enable this for Pixel3 along with panel driver (not part of this series) and DT changes can be found at: git.linaro.org/people/vinod.koul/kernel.git pixel/dsc_v3 Comments welcome! Changes since v2: - Fix comments by Dimitry except the dsc being global. - Move RM patch later for dependency on topology now - Add patch for mode valid callback for dsi_mgr - Add missing structure documentation patch - Fix errors in mode_3d changes - Rebase on v5.16-rc1 and test Changes since v1: - Fix various issues spotted by kbuildbot - Rebase to v5.15-rc3 - Remove unused fields and duplicate defines - Enable DSC blocks only when DSC is enabled - remove sdm845 feature mask, use 0 - Check for DSC in hw_ctl Changes since RFC: - Drop the DT binding patch as we derive the configuration from panel - Drop the drm api patch as we no longer need it (use pps drm api) - Fix comments raised by Dimitry - Add dsc parameters calculation from downstream Vinod Koul (13): drm/msm/dsi: add support for dsc data drm/msm/disp/dpu1: Add support for DSC drm/msm/disp/dpu1: Add support for DSC in pingpong block drm/msm/disp/dpu1: Add DSC for SDM845 to hw_catalog drm/msm/disp/dpu1: Don't use DSC with mode_3d drm/msm/disp/dpu1: Add DSC support in hw_ctl drm/msm/disp/dpu1: Add support for DSC in encoder drm/msm: Add missing structure documentation drm/msm/disp/dpu1: Add support for DSC in topology drm/msm/disp/dpu1: Add DSC support in RM drm/msm/dsi: add mode valid callback for dsi_mgr drm/msm/dsi: Add support for DSC configuration drm/msm/dsi: Pass DSC params to drm_panel drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 158 +++++++++- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 11 + .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 + .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 20 ++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 13 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 14 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 2 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 210 +++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h | 77 +++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 13 + .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 32 ++ .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 14 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 66 ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 1 + drivers/gpu/drm/msm/dsi/dsi.h | 2 + drivers/gpu/drm/msm/dsi/dsi.xml.h | 10 + drivers/gpu/drm/msm/dsi/dsi_host.c | 285 +++++++++++++++++- drivers/gpu/drm/msm/dsi/dsi_manager.c | 12 + drivers/gpu/drm/msm/msm_drv.h | 23 ++ include/drm/drm_panel.h | 7 + 22 files changed, 970 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h