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[82.127.83.212]) by mx.google.com with ESMTPSA id eu8sm1299618wib.21.2014.12.05.00.35.56 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 05 Dec 2014 00:35:56 -0800 (PST) From: Benjamin Gaignard To: dri-devel@lists.freedesktop.org, linaro-mm-sig@lists.linaro.org Subject: [PATCH 3/9] drm: sti: clear all mixer control Date: Fri, 5 Dec 2014 09:35:01 +0100 Message-Id: <1417768507-7538-4-git-send-email-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1417768507-7538-1-git-send-email-benjamin.gaignard@linaro.org> References: <1417768507-7538-1-git-send-email-benjamin.gaignard@linaro.org> Cc: Benjamin Gaignard X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: benjamin.gaignard@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.46 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Make sure that mixer control register is correctly reset before use it. Signed-off-by: Benjamin Gaignard --- drivers/gpu/drm/sti/sti_drm_crtc.c | 2 ++ drivers/gpu/drm/sti/sti_mixer.c | 9 +++++++++ drivers/gpu/drm/sti/sti_mixer.h | 1 + 3 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/sti/sti_drm_crtc.c b/drivers/gpu/drm/sti/sti_drm_crtc.c index d2ae0c0..e1e5550 100644 --- a/drivers/gpu/drm/sti/sti_drm_crtc.c +++ b/drivers/gpu/drm/sti/sti_drm_crtc.c @@ -37,6 +37,8 @@ static void sti_drm_crtc_prepare(struct drm_crtc *crtc) if (clk_prepare_enable(compo->clk_compo_aux)) DRM_INFO("Failed to prepare/enable compo_aux clk\n"); } + + sti_mixer_clear_all_layers(mixer); } static void sti_drm_crtc_commit(struct drm_crtc *crtc) diff --git a/drivers/gpu/drm/sti/sti_mixer.c b/drivers/gpu/drm/sti/sti_mixer.c index 79f369d..6bcdf3f 100644 --- a/drivers/gpu/drm/sti/sti_mixer.c +++ b/drivers/gpu/drm/sti/sti_mixer.c @@ -215,6 +215,15 @@ int sti_mixer_set_layer_status(struct sti_mixer *mixer, return 0; } +void sti_mixer_clear_all_layers(struct sti_mixer *mixer) +{ + u32 val; + + DRM_DEBUG_DRIVER("%s clear all layer\n", sti_mixer_to_str(mixer)); + val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL) & 0xFFFF0000; + sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val); +} + void sti_mixer_set_matrix(struct sti_mixer *mixer) { unsigned int i; diff --git a/drivers/gpu/drm/sti/sti_mixer.h b/drivers/gpu/drm/sti/sti_mixer.h index 8743721..750e1fd 100644 --- a/drivers/gpu/drm/sti/sti_mixer.h +++ b/drivers/gpu/drm/sti/sti_mixer.h @@ -39,6 +39,7 @@ struct sti_mixer *sti_mixer_create(struct device *dev, int id, int sti_mixer_set_layer_status(struct sti_mixer *mixer, struct sti_layer *layer, bool status); +void sti_mixer_clear_all_layers(struct sti_mixer *mixer); int sti_mixer_set_layer_depth(struct sti_mixer *mixer, struct sti_layer *layer); int sti_mixer_active_video_area(struct sti_mixer *mixer, struct drm_display_mode *mode);