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[131.252.210.177]) by mx.google.com with ESMTPS id u10si1359039pgp.222.2018.02.01.04.55.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 01 Feb 2018 04:55:29 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=cGOtJ730; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A4E496ED9F; Thu, 1 Feb 2018 12:55:26 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lf0-x244.google.com (mail-lf0-x244.google.com [IPv6:2a00:1450:4010:c07::244]) by gabe.freedesktop.org (Postfix) with ESMTPS id 08BAE6ED9F for ; Thu, 1 Feb 2018 12:55:25 +0000 (UTC) Received: by mail-lf0-x244.google.com with SMTP id x196so26035835lfd.12 for ; Thu, 01 Feb 2018 04:55:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yAMtyCJdps5O1j3rlHRae3yXUI5uzqnLp6Klq6l0G/E=; b=cGOtJ730fDKGrD9a3QnrBU7zAtI8v+tX0WOxnWvCf7isTSl8PKZDSguqOpSLzwTA33 P0tlsT17RbTq7z3ZBb+2jLbegzCqDfN/Em3kmxpaXQVSmnyO3k282vQJdqeIZhTtSZ8/ f50UEdD0v3wIbmJTq80Qu6zcUhKhbD6N4HT0A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yAMtyCJdps5O1j3rlHRae3yXUI5uzqnLp6Klq6l0G/E=; b=L7Nk8Utr5h7KdxlNG5Qv6SXa3gzoeQQfOmgP9Ri9IdlW6VxSrdd5q2hcGfwGlsOO+8 iv7R9ZWb+Rr+t2plvQLc5Gn02sUsEk9q1xvbJyAMgTzduVEIdTph6061mWgwT9Yi7XVH 44QtbrWq5416IOGxkQ7DLOJYpA0MuUg1MyFZt7Ffj3fSeO0qWKJ9aIOOGvN0W7a0RNey u1BcwLqQi1lBg6q+e+J7i4kBfxWQ50b4FPuuCNcsixje9CZmtPnuRJ/6DMSxrTkq5KbZ h3fpulRz4f3Wu9rp+gMj2RjMKeanOw6o+RA+I77T9kCGOBtzOstfW7wK0oUWZb0q6Zhu MVqw== X-Gm-Message-State: AKwxytcT0FW9jrMELElFALGyAC3WIz0shXNEFXIZ3q6Xgs7xUC5lDP14 Obxy8sGgtho4MV1DHjReszWvkw== X-Received: by 10.25.79.65 with SMTP id a1mr14786639lfk.97.1517489724308; Thu, 01 Feb 2018 04:55:24 -0800 (PST) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id a129sm4300792lfa.0.2018.02.01.04.55.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 01 Feb 2018 04:55:23 -0800 (PST) From: Linus Walleij To: Daniel Vetter , Jani Nikula , Sean Paul , Eric Anholt Subject: [PATCH 3/5 v2] drm/pl111: Support variants with broken clock divider Date: Thu, 1 Feb 2018 13:55:11 +0100 Message-Id: <20180201125513.5482-4-linus.walleij@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180201125513.5482-1-linus.walleij@linaro.org> References: <20180201125513.5482-1-linus.walleij@linaro.org> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The early Integrator CLCD synthesized in the Integrator CP and IM-PD1 FPGAs are broken: their clock dividers do not work properly. Support disabling the clock divider and drive the clock directly from the parent under these circumstances. Signed-off-by: Linus Walleij --- drivers/gpu/drm/pl111/pl111_display.c | 8 ++++++++ drivers/gpu/drm/pl111/pl111_drm.h | 3 +++ drivers/gpu/drm/pl111/pl111_versatile.c | 1 + 3 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/pl111/pl111_display.c b/drivers/gpu/drm/pl111/pl111_display.c index 55ada00ec974..4d4e38b4c9d5 100644 --- a/drivers/gpu/drm/pl111/pl111_display.c +++ b/drivers/gpu/drm/pl111/pl111_display.c @@ -138,6 +138,9 @@ static void pl111_display_enable(struct drm_simple_display_pipe *pipe, tim2 = readl(priv->regs + CLCD_TIM2); tim2 &= (TIM2_BCD | TIM2_PCD_LO_MASK | TIM2_PCD_HI_MASK); + if (priv->variant->broken_clockdivider) + tim2 |= TIM2_BCD; + if (mode->flags & DRM_MODE_FLAG_NHSYNC) tim2 |= TIM2_IHS; @@ -455,6 +458,11 @@ pl111_init_clock_divider(struct drm_device *drm) dev_err(drm->dev, "CLCD: unable to get clcdclk.\n"); return PTR_ERR(parent); } + /* If the clock divider is broken, use the parent directly */ + if (priv->variant->broken_clockdivider) { + priv->clk = parent; + return 0; + } parent_name = __clk_get_name(parent); spin_lock_init(&priv->tim2_lock); diff --git a/drivers/gpu/drm/pl111/pl111_drm.h b/drivers/gpu/drm/pl111/pl111_drm.h index c2f410f0b12e..f75c5d4645b2 100644 --- a/drivers/gpu/drm/pl111/pl111_drm.h +++ b/drivers/gpu/drm/pl111/pl111_drm.h @@ -38,6 +38,8 @@ struct drm_minor; * @is_pl110: this is the early PL110 variant * @external_bgr: this is the Versatile Pl110 variant with external * BGR/RGB routing + * @broken_clockdivider: the clock divider is broken and we need to + * use the supplied clock directly * @formats: array of supported pixel formats on this variant * @nformats: the length of the array of supported pixel formats */ @@ -45,6 +47,7 @@ struct pl111_variant_data { const char *name; bool is_pl110; bool external_bgr; + bool broken_clockdivider; const u32 *formats; unsigned int nformats; }; diff --git a/drivers/gpu/drm/pl111/pl111_versatile.c b/drivers/gpu/drm/pl111/pl111_versatile.c index 893d527fb42f..0f228543a97c 100644 --- a/drivers/gpu/drm/pl111/pl111_versatile.c +++ b/drivers/gpu/drm/pl111/pl111_versatile.c @@ -237,6 +237,7 @@ static const u32 pl110_versatile_pixel_formats[] = { static const struct pl111_variant_data pl110_integrator = { .name = "PL110 Integrator", .is_pl110 = true, + .broken_clockdivider = true, .formats = pl110_integrator_pixel_formats, .nformats = ARRAY_SIZE(pl110_integrator_pixel_formats), };