From patchwork Fri May 3 12:29:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 163315 Delivered-To: patch@linaro.org Received: by 2002:a92:7e86:0:0:0:0:0 with SMTP id q6csp546947ill; Fri, 3 May 2019 05:31:26 -0700 (PDT) X-Google-Smtp-Source: APXvYqx9VDuNXZ45jZFmxcDTODH8vYIXs5ePH/4g55z6pB8egs2Qu5cs/o53DsOKTXIKN33uj+ju X-Received: by 2002:a63:1d4f:: with SMTP id d15mr9522139pgm.347.1556886686155; Fri, 03 May 2019 05:31:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556886686; cv=none; d=google.com; s=arc-20160816; b=xLj7jzVkwilNTtkzQyLEyjlR+xOCgXDHRaXHBMxeU0F2WdEmkOMRZuaeQpixSR35PX ta3b50pUxPpJvqZ0C1MXqdRCUY+sFMb7GW7MvdPp27LlOgXWuZdLfkXwCGG6yiqQkbY8 N9tVyxCjmxiN/F2FXKc+MQU2Hcp52pDUfQ1hB0G/YcEYZ7aQMH9MJXiukOAtwgUmTJ9K 1n7SqIBR1rJZmQLxe6toRN2k+Bg2Dpf5LvhmEh6t/+ez76VDRiSunuaI3qrgNyO8onwX VfS6yWgcSWknBOLNdCQLc3MPNY7z8br9dLBLqhmiviFhcXU3CskWj2M0JR4tLVVU+yAl ZtPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:references:in-reply-to:message-id:date :subject:to:from:delivered-to; bh=uRi8TeQJvVgHFzgDWvjLqZciqy6YBvCEsEdsTlsU8h8=; b=G83a3DOhKaH08ItaZZRM+MBUScxE5xAn0dG5ii7ZYvaHRpg311JYvTuoTyh9XYExC2 bn/6nA6IkVyX7ZOm7CtTzC0UPzFfRfj/BQmVtSeSp1iqk28YHMurf8PuiubhbJZAI2sO dW8b/uPAKZfG2rq8uZ2zfZeduXMATXnoy4CkzmoNb+8+lGOpaZL/05q8KuPHwUxmwQaT u3RQHD+iTeTGfURKBQTNHqqB7VNwXgbCkuyiCjHD7/TTP4aHAeX1yBakdCJtn+PIS7eV yyF1RUujBIcZr3NrZ1C9vTvlEDG238BO6hj6zx4h/LRLxzc/1FZ2JB/K6tMhrncdnuRf KWaw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [2610:10:20:722:a800:ff:fe36:1795]) by mx.google.com with ESMTPS id e1si2352535pln.52.2019.05.03.05.31.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 May 2019 05:31:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) client-ip=2610:10:20:722:a800:ff:fe36:1795; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 00C2C89F2D; Fri, 3 May 2019 12:31:25 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by gabe.freedesktop.org (Postfix) with ESMTPS id 484E889F27 for ; Fri, 3 May 2019 12:31:23 +0000 (UTC) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x43CVKn7098049; Fri, 3 May 2019 07:31:20 -0500 Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x43CVKZK049567 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 3 May 2019 07:31:20 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 3 May 2019 07:31:18 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 3 May 2019 07:31:18 -0500 Received: from deskari.lan (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x43CUYu0002029; Fri, 3 May 2019 07:31:16 -0500 From: Tomi Valkeinen To: Andrzej Hajda , Laurent Pinchart , Lucas Stach , Andrey Gusakov , Philipp Zabel , Andrey Smirnov , Peter Ujfalusi , Jyri Sarha , Benoit Parrot , Subject: [PATCHv3 16/23] drm/bridge: tc358767: clean-up link training Date: Fri, 3 May 2019 15:29:42 +0300 Message-ID: <20190503122949.12266-17-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190503122949.12266-1-tomi.valkeinen@ti.com> References: <20190503122949.12266-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1556886680; bh=WNy+ddXzZfHGmEezJTxjLF2V4lhmNzlS5deYA8ygipM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=NIy94lJvZMH9qkbzLsW7b7w1uK75e1w1iB2LG2ivP2yFw5t5wBD9D32i4oArTmmst KhkMl8Fg2MKftPdTXnaNaZ0Z7r0QKdrtO7V5UF6Rv7kExvuXB/n/OvOikwX5/aQxRH 6Ftf3o5DWfxMcPjZPhVy/HDCdcDCsnrUW5+yBy9Y= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tomi Valkeinen Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The current link training code does unnecessary retry-loops, and does extra writes to the registers. It is easier to follow the flow and ensure it's similar to Toshiba's documentation if we deal with LT inside tc_main_link_enable() function. This patch adds tc_wait_link_training() which handles waiting for the LT phase to finish, and does the necessary LT register setups in tc_main_link_enable, without extra loops. Signed-off-by: Tomi Valkeinen Reviewed-by: Andrzej Hajda --- drivers/gpu/drm/bridge/tc358767.c | 136 +++++++++++++----------------- 1 file changed, 60 insertions(+), 76 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c index 2cec06520fcf..86175e8d01b3 100644 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@ -740,84 +740,24 @@ static int tc_set_video_mode(struct tc_data *tc, return ret; } -static int tc_link_training(struct tc_data *tc, int pattern) +static int tc_wait_link_training(struct tc_data *tc) { - const char * const *errors; - u32 srcctrl = tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS | - DP0_SRCCTRL_AUTOCORRECT; - int timeout; - int retry; + u32 timeout = 1000; u32 value; int ret; - if (pattern == DP_TRAINING_PATTERN_1) { - srcctrl |= DP0_SRCCTRL_TP1; - errors = training_pattern1_errors; - } else { - srcctrl |= DP0_SRCCTRL_TP2; - errors = training_pattern2_errors; - } - - /* Set DPCD 0x102 for Training Part 1 or 2 */ - tc_write(DP0_SNKLTCTRL, DP_LINK_SCRAMBLING_DISABLE | pattern); - - tc_write(DP0_LTLOOPCTRL, - (0x0f << 28) | /* Defer Iteration Count */ - (0x0f << 24) | /* Loop Iteration Count */ - (0x0d << 0)); /* Loop Timer Delay */ - - retry = 5; do { - /* Set DP0 Training Pattern */ - tc_write(DP0_SRCCTRL, srcctrl); - - /* Enable DP0 to start Link Training */ - tc_write(DP0CTL, DP_EN); - - /* wait */ - timeout = 1000; - do { - tc_read(DP0_LTSTAT, &value); - udelay(1); - } while ((!(value & LT_LOOPDONE)) && (--timeout)); - if (timeout == 0) { - dev_err(tc->dev, "Link training timeout!\n"); - } else { - int pattern = (value >> 11) & 0x3; - int error = (value >> 8) & 0x7; - - dev_dbg(tc->dev, - "Link training phase %d done after %d uS: %s\n", - pattern, 1000 - timeout, errors[error]); - if (pattern == DP_TRAINING_PATTERN_1 && error == 0) - break; - if (pattern == DP_TRAINING_PATTERN_2) { - value &= LT_CHANNEL1_EQ_BITS | - LT_INTERLANE_ALIGN_DONE | - LT_CHANNEL0_EQ_BITS; - /* in case of two lanes */ - if ((tc->link.base.num_lanes == 2) && - (value == (LT_CHANNEL1_EQ_BITS | - LT_INTERLANE_ALIGN_DONE | - LT_CHANNEL0_EQ_BITS))) - break; - /* in case of one line */ - if ((tc->link.base.num_lanes == 1) && - (value == (LT_INTERLANE_ALIGN_DONE | - LT_CHANNEL0_EQ_BITS))) - break; - } - } - /* restart */ - tc_write(DP0CTL, 0); - usleep_range(10, 20); - } while (--retry); - if (retry == 0) { - dev_err(tc->dev, "Failed to finish training phase %d\n", - pattern); + udelay(1); + tc_read(DP0_LTSTAT, &value); + } while ((!(value & LT_LOOPDONE)) && (--timeout)); + + if (timeout == 0) { + dev_err(tc->dev, "Link training timeout waiting for LT_LOOPDONE!\n"); + return -ETIMEDOUT; } - return 0; + return (value >> 8) & 0x7; + err: return ret; } @@ -927,7 +867,7 @@ static int tc_main_link_enable(struct tc_data *tc) if (tmp[0] != tc->assr) { dev_dbg(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n", - tc->assr); + tc->assr); /* trying with disabled scrambler */ tc->link.scrambler_dis = true; } @@ -953,13 +893,57 @@ static int tc_main_link_enable(struct tc_data *tc) if (ret < 0) goto err_dpcd_write; - ret = tc_link_training(tc, DP_TRAINING_PATTERN_1); - if (ret) + /* Clock-Recovery */ + + /* Set DPCD 0x102 for Training Pattern 1 */ + tc_write(DP0_SNKLTCTRL, DP_LINK_SCRAMBLING_DISABLE | + DP_TRAINING_PATTERN_1); + + tc_write(DP0_LTLOOPCTRL, + (15 << 28) | /* Defer Iteration Count */ + (15 << 24) | /* Loop Iteration Count */ + (0xd << 0)); /* Loop Timer Delay */ + + tc_write(DP0_SRCCTRL, tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS | + DP0_SRCCTRL_AUTOCORRECT | DP0_SRCCTRL_TP1); + + /* Enable DP0 to start Link Training */ + tc_write(DP0CTL, + ((tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) ? EF_EN : 0) | + DP_EN); + + /* wait */ + ret = tc_wait_link_training(tc); + if (ret < 0) goto err; - ret = tc_link_training(tc, DP_TRAINING_PATTERN_2); - if (ret) + if (ret) { + dev_err(tc->dev, "Link training phase 1 failed: %s\n", + training_pattern1_errors[ret]); + ret = -ENODEV; goto err; + } + + /* Channel Equalization */ + + /* Set DPCD 0x102 for Training Pattern 2 */ + tc_write(DP0_SNKLTCTRL, DP_LINK_SCRAMBLING_DISABLE | + DP_TRAINING_PATTERN_2); + + tc_write(DP0_SRCCTRL, tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS | + DP0_SRCCTRL_AUTOCORRECT | DP0_SRCCTRL_TP2); + + /* wait */ + ret = tc_wait_link_training(tc); + if (ret < 0) + goto err; + + if (ret) { + dev_err(tc->dev, "Link training phase 2 failed: %s\n", + training_pattern2_errors[ret]); + ret = -ENODEV; + goto err; + } /* * Toshiba's documentation suggests to first clear DPCD 0x102, then