From patchwork Tue Nov 16 06:22:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 519181 Delivered-To: patch@linaro.org Received: by 2002:ac0:c605:0:0:0:0:0 with SMTP id p5csp6710522imj; Mon, 15 Nov 2021 22:23:47 -0800 (PST) X-Google-Smtp-Source: ABdhPJw/UoqlXP8sUjq7fP9yIZojpBL2UMlshn79HfhibBOyuZ2x31z1j4s+gzBhuJ/Unld+Yd7S X-Received: by 2002:a17:902:c410:b0:142:2506:cb5b with SMTP id k16-20020a170902c41000b001422506cb5bmr42342896plk.36.1637043827043; Mon, 15 Nov 2021 22:23:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1637043827; cv=none; d=google.com; s=arc-20160816; b=AavN4G6S6AFbiwiKaXkrI2qpXMxwqk5Vd0wqqWWnDjMfmX/FixTc0z3i2yEVKW89zb urEV5xiKrPoIym828x9jwugqIS2OqX47M4FKEv+PaGlzP9poMiNYUXqQNyQx+D79w0dg Lu7XFT5h4kQNEZ1avzJ9c/QYs196P15pesr6qRAcSu8Gi7ITA+ZHi99TYZUxcWdgg4kK mKcPMonkKIHLg2+4sA1pbaHCBa7id0dyWJZUV6ggJv6V2T6PQ1D2Izu2qxeemQWacWsm kctU89/T5/a9NzKyDusPTaMrvfzPIWKIFE2A/SNKxR1HtvMEKvVk4yDjG/s4qp02uQHE dU7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature:delivered-to; bh=2JObKv49j+TwGM/Gk1Y8n2qQ4vxazY2VKBjTGOyq+m0=; b=ix0KqEN15VuIIIi/HA3pwIqthgqK7iwzm/QenkvjBaHjlFW/YLmUqcv6n6FtZvMSmE T04K/PYH70HFdSyQvT8oBUYDTGgSpEeoEyEPAWl/1rhw1cg5LuCgZrTOCC04+wkXVZFJ npPNgBOeaOZdZms/EVSyCIaCxSWnmDF5SKRjRGTNEGbDxCjp5ehiAzex3ZfIK7J5zSej a3e2B6R62QBkkCW2t5DhdOCOah3sOAhSn1vwTrVP/E/BUbnZkx2tqXrfJ7aXXFUxbE2Z Hb/kvi0YAFhp6SFSuWaCYh6ftPyPl57rJLc/8DEcCUf3Zbw2xGWXSOS6SKXnrHrnoDmQ kK7Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@kernel.org header.s=k20201202 header.b=B2LekTiS; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [131.252.210.177]) by mx.google.com with ESMTPS id m6si27813926pll.75.2021.11.15.22.23.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Nov 2021 22:23:47 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; dkim=fail header.i=@kernel.org header.s=k20201202 header.b=B2LekTiS; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5DA0F6EA24; Tue, 16 Nov 2021 06:23:45 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by gabe.freedesktop.org (Postfix) with ESMTPS id C2F4F6EA21; Tue, 16 Nov 2021 06:23:43 +0000 (UTC) Received: by mail.kernel.org (Postfix) with ESMTPSA id 30EB461A79; Tue, 16 Nov 2021 06:23:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1637043823; bh=Yr/dwVkvZofCAhC+sJHFNwq4JU5WQlv+/LDtwBUNTxw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=B2LekTiSm/u3gmWKpn1ICGtW80a1IGeHlGdKprMX2qEpZCoD/dm7J6A+1HccV33sm dUWsZeh3zeoYywy73CfbmtmuXvOgcIHv0YY3ESuH/mOyOVzz8gzWhtXosnIpNnD+wa ARPeozt7tUPfiWWF9q6qbTp0i3EYgZjhxQXstQjBEiJ4QikM+x5WnjwK7KfvKy0f3c QWBe6TGvgjll7mM3JL0tq++puBFkJyQ2I1tZB9YZuQHNkz/tQmfJYAsR6uCQGR94V2 gcQiiJqo88OCY/AiNd3+q0xt5FIC1OomWAGCPDexqCbgB09JmWGgdpUDK70EpcxV+S 0rDHVR9Zb4CNA== From: Vinod Koul To: Rob Clark Subject: [PATCH v3 06/13] drm/msm/disp/dpu1: Add DSC support in hw_ctl Date: Tue, 16 Nov 2021 11:52:49 +0530 Message-Id: <20211116062256.2417186-7-vkoul@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211116062256.2417186-1-vkoul@kernel.org> References: <20211116062256.2417186-1-vkoul@kernel.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jonathan Marek , Jeffrey Hugo , David Airlie , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Abhinav Kumar , Bjorn Andersson , Vinod Koul , dri-devel@lists.freedesktop.org, Dmitry Baryshkov , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Later gens of hardware have DSC bits moved to hw_ctl, so configure these bits so that DSC would work there as well Signed-off-by: Vinod Koul Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index 36831457a91b..66b0c44118d8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -25,6 +25,8 @@ #define CTL_MERGE_3D_ACTIVE 0x0E4 #define CTL_INTF_ACTIVE 0x0F4 #define CTL_MERGE_3D_FLUSH 0x100 +#define CTL_DSC_ACTIVE 0x0E8 +#define CTL_DSC_FLUSH 0x104 #define CTL_INTF_FLUSH 0x110 #define CTL_INTF_MASTER 0x134 #define CTL_FETCH_PIPE_ACTIVE 0x0FC @@ -34,6 +36,7 @@ #define DPU_REG_RESET_TIMEOUT_US 2000 #define MERGE_3D_IDX 23 +#define DSC_IDX 22 #define INTF_IDX 31 #define CTL_INVALID_BIT 0xffff @@ -120,7 +123,6 @@ static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx) static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) { - if (ctx->pending_flush_mask & BIT(MERGE_3D_IDX)) DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH, ctx->pending_merge_3d_flush_mask); @@ -498,6 +500,9 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, u32 intf_active = 0; u32 mode_sel = 0; + if (cfg->dsc) + DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, cfg->dsc); + if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD) mode_sel |= BIT(17); @@ -509,6 +514,10 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, if (cfg->merge_3d) DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, BIT(cfg->merge_3d - MERGE_3D_0)); + if (cfg->dsc) { + DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, cfg->dsc); + DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc); + } } static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,