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[209.132.180.131]) by mx.google.com with ESMTPS id of2si14348815pbb.156.2014.07.01.03.08.04 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 01 Jul 2014 03:08:04 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-371569-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 3172 invoked by alias); 1 Jul 2014 10:07:24 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 3052 invoked by uid 89); 1 Jul 2014 10:07:23 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-we0-f170.google.com Received: from mail-we0-f170.google.com (HELO mail-we0-f170.google.com) (74.125.82.170) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Tue, 01 Jul 2014 10:07:14 +0000 Received: by mail-we0-f170.google.com with SMTP id w61so9342704wes.15 for ; Tue, 01 Jul 2014 03:07:10 -0700 (PDT) X-Received: by 10.194.78.141 with SMTP id b13mr1983521wjx.111.1404209230670; Tue, 01 Jul 2014 03:07:10 -0700 (PDT) Received: from gnx2647.cec-lab.gnb.st.com ([2a01:e35:2e1d:eaf0:210:75ff:fe1a:c986]) by mx.google.com with ESMTPSA id kr6sm47178017wjb.16.2014.07.01.03.07.09 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 01 Jul 2014 03:07:10 -0700 (PDT) From: Christophe Lyon To: gcc-patches@gcc.gnu.org Subject: [Patch ARM-AArch64/testsuite v2 05/21] Add comparison operators with floating-point operands: vcage, vcagt, vcale and cvalt. Date: Tue, 1 Jul 2014 12:05:58 +0200 Message-Id: <1404209174-25364-6-git-send-email-christophe.lyon@linaro.org> In-Reply-To: <1404209174-25364-1-git-send-email-christophe.lyon@linaro.org> References: <1404209174-25364-1-git-send-email-christophe.lyon@linaro.org> X-IsSubscribed: yes X-Original-Sender: christophe.lyon@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2607:f8b0:400c:c01::233 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 7af7fd0..3c25af1 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,13 @@ 2014-06-30 Christophe Lyon + * gcc.target/aarch64/neon-intrinsics/cmp_fp_op.inc: New file. + * gcc.target/aarch64/neon-intrinsics/vcage.c: Likewise. + * gcc.target/aarch64/neon-intrinsics/vcagt.c: Likewise. + * gcc.target/aarch64/neon-intrinsics/vcale.c: Likewise. + * gcc.target/aarch64/neon-intrinsics/vcalt.c: Likewise. + +2014-06-30 Christophe Lyon + * gcc.target/aarch64/neon-intrinsics/cmp_op.inc: New file. * gcc.target/aarch64/neon-intrinsics/vceq.c: Likewise. * gcc.target/aarch64/neon-intrinsics/vcge.c: Likewise. diff --git a/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/cmp_fp_op.inc b/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/cmp_fp_op.inc new file mode 100644 index 0000000..33451d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/cmp_fp_op.inc @@ -0,0 +1,75 @@ +/* Template file for the validation of comparison operator with + floating-point support. + + This file is meant to be included by the relevant test files, which + have to define the intrinsic family to test. If a given intrinsic + supports variants which are not supported by all the other + operators, these can be tested by providing a definition for + EXTRA_TESTS. */ + +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +/* Additional expected results declaration, they are initialized in + each test file. */ +extern ARRAY(expected2, uint, 32, 2); +extern ARRAY(expected2, uint, 32, 4); + +#define FNNAME1(NAME) exec_ ## NAME +#define FNNAME(NAME) FNNAME1(NAME) + +void FNNAME (INSN_NAME) (void) +{ + /* Basic test: y=vcomp(x1,x2), then store the result. */ +#define TEST_VCOMP1(INSN, Q, T1, T2, T3, W, N) \ + VECT_VAR(vector_res, T3, W, N) = \ + INSN##Q##_##T2##W(VECT_VAR(vector, T1, W, N), \ + VECT_VAR(vector2, T1, W, N)); \ + vst1##Q##_u##W(VECT_VAR(result, T3, W, N), VECT_VAR(vector_res, T3, W, N)) + +#define TEST_VCOMP(INSN, Q, T1, T2, T3, W, N) \ + TEST_VCOMP1(INSN, Q, T1, T2, T3, W, N) + + DECL_VARIABLE(vector, float, 32, 2); + DECL_VARIABLE(vector, float, 32, 4); + DECL_VARIABLE(vector2, float, 32, 2); + DECL_VARIABLE(vector2, float, 32, 4); + DECL_VARIABLE(vector_res, uint, 32, 2); + DECL_VARIABLE(vector_res, uint, 32, 4); + + clean_results (); + + /* Initialize input "vector" from "buffer". */ + VLOAD(vector, buffer, , float, f, 32, 2); + VLOAD(vector, buffer, q, float, f, 32, 4); + + /* Choose init value arbitrarily, will be used for vector + comparison. */ + VDUP(vector2, , float, f, 32, 2, -16.0f); + VDUP(vector2, q, float, f, 32, 4, -14.0f); + + /* Apply operator named INSN_NAME. */ + TEST_VCOMP(INSN_NAME, , float, f, uint, 32, 2); + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, ""); + + TEST_VCOMP(INSN_NAME, q, float, f, uint, 32, 4); + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, ""); + + /* Test again, with different input values. */ + VDUP(vector2, , float, f, 32, 2, -10.0f); + VDUP(vector2, q, float, f, 32, 4, 10.0f); + + TEST_VCOMP(INSN_NAME, , float, f, uint, 32, 2); + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected2, ""); + + TEST_VCOMP(INSN_NAME, q, float, f, uint, 32, 4); + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected2,""); +} + +int main (void) +{ + FNNAME (INSN_NAME) (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/vcage.c b/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/vcage.c new file mode 100644 index 0000000..219d03f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/vcage.c @@ -0,0 +1,52 @@ +#define INSN_NAME vcage +#define TEST_MSG "VCAGE/VCAGEQ" + +#include "cmp_fp_op.inc" + +/* Expected results. */ +VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,int,16,4) [] = { 0x333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 }; +VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; +VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,uint,16,4) [] = { 0x333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffff, 0x0 }; +VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; +VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,int,16,8) [] = { 0x333, 0x3333, 0x3333, 0x3333, + 0x333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,int,32,4) [] = { 0x33333333, 0x33333333, + 0x33333333, 0x33333333 }; +VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, + 0x3333333333333333 }; +VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,uint,16,8) [] = { 0x333, 0x3333, 0x3333, 0x3333, + 0x333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffffff, 0xffffffff, + 0xffffffff, 0x0 }; +VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, + 0x3333333333333333 }; +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, + 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, + 0x33333333, 0x33333333 }; + +VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xffffffff, 0xffffffff }; +VECT_VAR_DECL(expected2,uint,32,4) [] = { 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff }; diff --git a/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/vcagt.c b/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/vcagt.c new file mode 100644 index 0000000..ed62c85 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/vcagt.c @@ -0,0 +1,51 @@ +#define INSN_NAME vcagt +#define TEST_MSG "VCAGT/VCAGTQ" + +#include "cmp_fp_op.inc" + +/* Expected results. */ +VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,int,16,4) [] = { 0x333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 }; +VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; +VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,uint,16,4) [] = { 0x333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,uint,32,2) [] = { 0x0, 0x0 }; +VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; +VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,int,16,8) [] = { 0x333, 0x3333, 0x3333, 0x3333, + 0x333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffffff, 0xffffffff, 0x0, 0x0 }; +VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, + 0x3333333333333333 }; +VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,uint,16,8) [] = { 0x333, 0x3333, 0x3333, 0x3333, + 0x333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffffff, 0xffffffff, + 0x0, 0x0 }; +VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, + 0x3333333333333333 }; +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, + 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, + 0x33333333, 0x33333333 }; + +VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xffffffff, 0xffffffff }; +VECT_VAR_DECL(expected2,uint,32,4) [] = { 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff }; diff --git a/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/vcale.c b/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/vcale.c new file mode 100644 index 0000000..cc83a39 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/vcale.c @@ -0,0 +1,49 @@ +#define INSN_NAME vcale +#define TEST_MSG "VCALE/VCALEQ" + +#include "cmp_fp_op.inc" + +/* Expected results. */ +VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,int,16,4) [] = { 0x333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 }; +VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; +VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,uint,16,4) [] = { 0x333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffff, 0xffffffff }; +VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; +VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,int,16,8) [] = { 0x333, 0x3333, 0x3333, 0x3333, + 0x333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffffff, 0xffffffff, 0x0, 0x0 }; +VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, + 0x3333333333333333 }; +VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,uint,16,8) [] = { 0x333, 0x3333, 0x3333, 0x3333, + 0x333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,uint,32,4) [] = { 0x0, 0x0, 0xffffffff, 0xffffffff }; +VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, + 0x3333333333333333 }; +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, + 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, + 0x33333333, 0x33333333 }; + +VECT_VAR_DECL(expected2,uint,32,2) [] = { 0x0, 0x0 }; +VECT_VAR_DECL(expected2,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 }; diff --git a/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/vcalt.c b/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/vcalt.c new file mode 100644 index 0000000..a60536e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/vcalt.c @@ -0,0 +1,49 @@ +#define INSN_NAME vcalt +#define TEST_MSG "VCALT/VCALTQ" + +#include "cmp_fp_op.inc" + +/* Expected results. */ +VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,int,16,4) [] = { 0x333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 }; +VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; +VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,uint,16,4) [] = { 0x333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,uint,32,2) [] = { 0x0, 0xffffffff }; +VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; +VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,int,16,8) [] = { 0x333, 0x3333, 0x3333, 0x3333, + 0x333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffffff, 0xffffffff, 0x0, 0x0 }; +VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, + 0x3333333333333333 }; +VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,uint,16,8) [] = { 0x333, 0x3333, 0x3333, 0x3333, + 0x333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,uint,32,4) [] = { 0x0, 0x0, 0x0, 0xffffffff }; +VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, + 0x3333333333333333 }; +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, + 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, + 0x33333333, 0x33333333 }; + +VECT_VAR_DECL(expected2,uint,32,2) [] = { 0x0, 0x0 }; +VECT_VAR_DECL(expected2,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };