From patchwork Tue Jan 13 15:17:59 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Lyon X-Patchwork-Id: 43019 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-lb0-f199.google.com (mail-lb0-f199.google.com [209.85.217.199]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 52D6B20DE8 for ; Tue, 13 Jan 2015 15:19:30 +0000 (UTC) Received: by mail-lb0-f199.google.com with SMTP id z12sf2023871lbi.2 for ; Tue, 13 Jan 2015 07:19:29 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:mailing-list :precedence:list-id:list-unsubscribe:list-archive:list-post :list-help:sender:delivered-to:from:to:subject:date:message-id :in-reply-to:references:x-original-sender :x-original-authentication-results; bh=9TtYDdwu7l5wj6nUPTh5hSQ1hq2Ph8O30MdD97zkHo0=; b=W4B8/sVeLrN0ggrd8RR3jOonG/q2kdX91atHRx58+k70wMUnFkbDuM0y1KmBpzaz4X OYwo+bdK1MmVT2aZqv5YxqLECGR28e+A0Xw+PyZp9UA/udqKCEmFj1/QJKprFvJm05ef 2+zWJlmSdQeAuBEKdcvWPwCamfhI36+05OPg5S90fJh5axM58Zwj8hWNqgIRbiNSuvPK HK1S5DK4qoRuEFnFhk7aTYpFe2DLbgGjB7V13bOOd72aXJm5ORmWWRMyPKgbBMLKVY/z noYQyN227wWKFdykassvDGJdUVRlYCGAVnGyrjQETrFeR4ShmvGBHC4c7Gdq2L78zoCZ WWdQ== X-Gm-Message-State: ALoCoQk8EdE8Fi+YuOppyD71FIlbsB9mHcXEBsWRZcK6j+awGMwjaJnCJGuTvE5MCKn+sn3jn1+M X-Received: by 10.194.92.34 with SMTP id cj2mr407977wjb.5.1421162369220; Tue, 13 Jan 2015 07:19:29 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.28.41 with SMTP id y9ls10109lag.54.gmail; Tue, 13 Jan 2015 07:19:29 -0800 (PST) X-Received: by 10.152.87.12 with SMTP id t12mr42783081laz.31.1421162369062; Tue, 13 Jan 2015 07:19:29 -0800 (PST) Received: from mail-lb0-x234.google.com (mail-lb0-x234.google.com. [2a00:1450:4010:c04::234]) by mx.google.com with ESMTPS id pr6si24561552lbb.30.2015.01.13.07.19.29 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 13 Jan 2015 07:19:29 -0800 (PST) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c04::234 as permitted sender) client-ip=2a00:1450:4010:c04::234; Received: by mail-lb0-f180.google.com with SMTP id l4so3070090lbv.11 for ; Tue, 13 Jan 2015 07:19:29 -0800 (PST) X-Received: by 10.152.5.226 with SMTP id v2mr43017104lav.34.1421162368898; Tue, 13 Jan 2015 07:19:28 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.9.200 with SMTP id c8csp1413438lbb; Tue, 13 Jan 2015 07:19:27 -0800 (PST) X-Received: by 10.66.255.99 with SMTP id ap3mr51329424pad.55.1421162366996; Tue, 13 Jan 2015 07:19:26 -0800 (PST) Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id qy7si27372898pab.128.2015.01.13.07.19.25 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 13 Jan 2015 07:19:26 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-389027-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 22425 invoked by alias); 13 Jan 2015 15:18:57 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 22386 invoked by uid 89); 13 Jan 2015 15:18:55 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-wg0-f50.google.com Received: from mail-wg0-f50.google.com (HELO mail-wg0-f50.google.com) (74.125.82.50) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Tue, 13 Jan 2015 15:18:50 +0000 Received: by mail-wg0-f50.google.com with SMTP id a1so3541023wgh.9 for ; Tue, 13 Jan 2015 07:18:47 -0800 (PST) X-Received: by 10.180.7.201 with SMTP id l9mr5323238wia.80.1421162326706; Tue, 13 Jan 2015 07:18:46 -0800 (PST) Received: from babel.clyon.hd.free.fr (vig38-2-82-225-222-175.fbx.proxad.net. [82.225.222.175]) by mx.google.com with ESMTPSA id jr4sm26100313wjc.20.2015.01.13.07.18.45 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 13 Jan 2015 07:18:45 -0800 (PST) From: Christophe Lyon To: gcc-patches@gcc.gnu.org Subject: [[ARM/AArch64][testsuite] 01/36] Add explicit dependency on Neon Cumulative Saturation flag (QC). Date: Tue, 13 Jan 2015 16:17:59 +0100 Message-Id: <1421162314-25779-2-git-send-email-christophe.lyon@linaro.org> In-Reply-To: <1421162314-25779-1-git-send-email-christophe.lyon@linaro.org> References: <1421162314-25779-1-git-send-email-christophe.lyon@linaro.org> X-IsSubscribed: yes X-Original-Sender: christophe.lyon@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c04::234 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 __set_neon_cumulative_sat() modifies the contents on the QC flag, and some intrinsics do so too: this patch adds the explicit dependency on the asm statement, to avoid code reordering or removal. When writing QC, the asm statement now has a fake input dependency, which is the output of the intrinsic being tested. Modifying the __set_neon_cumulative_sat macro is necessary, to be able to accept all the possible input types. Update the generic code in unary_sat_op.inc and binary_sat_op.inc accordingly. * gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h (Set_Neon_Cumulative_Sat): Add parameter. (__set_neon_cumulative_sat): Support new parameter. * gcc.target/aarch64/advsimd-intrinsics/binary_sat_op.inc (TEST_BINARY_SAT_OP1): Call Set_Neon_Cumulative_Sat with new argument. * gcc.target/aarch64/advsimd-intrinsics/unary_sat_op.inc (TEST_UNARY_SAT_OP1): Call Set_Neon_Cumulative_Sat with new argument. diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h index 8ea1f26..6464c66 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h @@ -255,7 +255,11 @@ typedef union { #endif /* __ORDER_BIG_ENDIAN__ */ #define Neon_Cumulative_Sat __read_neon_cumulative_sat() -#define Set_Neon_Cumulative_Sat(x) __set_neon_cumulative_sat((x)) +/* We need a fake dependency to ensure correct ordering of asm + statements to preset the QC flag value, and Neon operators writing + to QC. */ +#define Set_Neon_Cumulative_Sat(x, depend) \ + __set_neon_cumulative_sat((x), (depend)) #if defined(__aarch64__) static volatile int __read_neon_cumulative_sat (void) { @@ -263,13 +267,12 @@ static volatile int __read_neon_cumulative_sat (void) { asm volatile ("mrs %0,fpsr" : "=r" (_afpscr_for_qc)); return _afpscr_for_qc.b.QC; } -static void __set_neon_cumulative_sat (int x) { - _ARM_FPSCR _afpscr_for_qc; - asm volatile ("mrs %0,fpsr" : "=r" (_afpscr_for_qc)); - _afpscr_for_qc.b.QC = x; - asm volatile ("msr fpsr,%0" : : "r" (_afpscr_for_qc)); - return; -} +#define __set_neon_cumulative_sat(x, depend) { \ + _ARM_FPSCR _afpscr_for_qc; \ + asm volatile ("mrs %0,fpsr" : "=r" (_afpscr_for_qc)); \ + _afpscr_for_qc.b.QC = x; \ + asm volatile ("msr fpsr,%1" : "=X" (depend) : "r" (_afpscr_for_qc)); \ + } #else static volatile int __read_neon_cumulative_sat (void) { _ARM_FPSCR _afpscr_for_qc; @@ -277,13 +280,12 @@ static volatile int __read_neon_cumulative_sat (void) { return _afpscr_for_qc.b.QC; } -static void __set_neon_cumulative_sat (int x) { - _ARM_FPSCR _afpscr_for_qc; - asm volatile ("vmrs %0,fpscr" : "=r" (_afpscr_for_qc)); - _afpscr_for_qc.b.QC = x; - asm volatile ("vmsr fpscr,%0" : : "r" (_afpscr_for_qc)); - return; -} +#define __set_neon_cumulative_sat(x, depend) { \ + _ARM_FPSCR _afpscr_for_qc; \ + asm volatile ("vmrs %0,fpscr" : "=r" (_afpscr_for_qc)); \ + _afpscr_for_qc.b.QC = x; \ + asm volatile ("vmsr fpscr,%1" : "=X" (depend) : "r" (_afpscr_for_qc)); \ + } #endif /* Declare expected cumulative saturation results, one for each diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_sat_op.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_sat_op.inc index 35d7701..c09a468 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_sat_op.inc +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_sat_op.inc @@ -18,7 +18,7 @@ void FNNAME (INSN_NAME) (void) /* vector_res = OP(vector1,vector2), then store the result. */ #define TEST_BINARY_SAT_OP1(INSN, Q, T1, T2, W, N, EXPECTED_CUMULATIVE_SAT, CMT) \ - Set_Neon_Cumulative_Sat(0); \ + Set_Neon_Cumulative_Sat(0, VECT_VAR(vector_res, T1, W, N)); \ VECT_VAR(vector_res, T1, W, N) = \ INSN##Q##_##T2##W(VECT_VAR(vector1, T1, W, N), \ VECT_VAR(vector2, T1, W, N)); \ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_sat_op.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_sat_op.inc index 3f6d984..0da1426 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_sat_op.inc +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_sat_op.inc @@ -17,7 +17,7 @@ void FNNAME (INSN_NAME) (void) { /* y=OP(x), then store the result. */ #define TEST_UNARY_SAT_OP1(INSN, Q, T1, T2, W, N, EXPECTED_CUMULATIVE_SAT, CMT) \ - Set_Neon_Cumulative_Sat(0); \ + Set_Neon_Cumulative_Sat(0, VECT_VAR(vector_res, T1, W, N)); \ VECT_VAR(vector_res, T1, W, N) = \ INSN##Q##_##T2##W(VECT_VAR(vector, T1, W, N)); \ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \