From patchwork Fri Dec 4 19:42:29 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Greenhalgh X-Patchwork-Id: 57723 Delivered-To: patch@linaro.org Received: by 10.112.155.196 with SMTP id vy4csp759003lbb; Fri, 4 Dec 2015 11:42:53 -0800 (PST) X-Received: by 10.67.7.101 with SMTP id db5mr24043707pad.53.1449258173003; Fri, 04 Dec 2015 11:42:53 -0800 (PST) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id y63si21172856pfa.117.2015.12.04.11.42.52 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Dec 2015 11:42:52 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-416454-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-return-416454-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-416454-patch=linaro.org@gcc.gnu.org; dkim=pass header.i=@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; q=dns; s=default; b=jsqKf05LhPK3ldxwwpgUmyz3wU2l1B/MqGa5LHc///P4LEVMlY g20fKI/fdT7k4sguNamgk620U47CxWk1phWQKZFxTQYEmRovPU5mf2H11G7J++bj aF8NPCxJkRZ6ozVa1Ft+vAybteHLnpjkzZ6Zuq8KsH5WteM/80qlKFbik= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; s= default; bh=+ZkCrt12mi2okxYFhWpNKLimGn8=; b=SyVQWIhlLN1UpnFBKnjG 14jWJNCfb3LypEeWMC+UzNz4rYJmI6jFUzmJfNWOAw5MZmzfTTSNwgFgp9ngaJBN svD3e2kjf4orPYlX27qY0vx806WicYUzR1bvI6M0tY645SmJlW3l4sIjynJtOLlI MFTkObSUhBrMZKEzFGNS198= Received: (qmail 56404 invoked by alias); 4 Dec 2015 19:42:41 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 56395 invoked by uid 89); 4 Dec 2015 19:42:40 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 04 Dec 2015 19:42:39 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-34-PIEm389WTcOm-0RCCCyzkw-1; Fri, 04 Dec 2015 19:42:34 +0000 Received: from e107456-lin.cambridge.arm.com ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 4 Dec 2015 19:42:33 +0000 From: James Greenhalgh To: gcc-patches@gcc.gnu.org Cc: richard.earnshaw@arm.com, marcus.shawcroft@arm.com, wilco.dijkstra@arm.com Subject: [AArch64] Add register constraints to add3_pluslong Date: Fri, 4 Dec 2015 19:42:29 +0000 Message-Id: <1449258149-4266-1-git-send-email-james.greenhalgh@arm.com> MIME-Version: 1.0 X-MC-Unique: PIEm389WTcOm-0RCCCyzkw-1 X-IsSubscribed: yes Hi, This patch fixes a bug I spotted in the add3_pluslong insn_and_split pattern. We need to give register constraints, otherwise the register allocator can do whatever it likes. This manifests as an ICE on AArch64 with -mabi=ilp32: gcc foo.c -O2 -mabi=ilp32 error: could not split insn } ^ (insn:TI 85 95 7 (set (mem/c:DI (plus:DI (reg/f:DI 29 x29) (const_int 40 [0x28])) [1 %sfp+-65528 S8 A64]) (plus:DI (plus:DI (reg/f:DI 29 x29) (const_int 16 [0x10])) (const_int 65552 [0x10010]))) foo.c:7 95 {*adddi3_pluslong} (nil)) The patch simply constrains the pattern to use w/x registers. Bootstrapped on aarch64-none-linux-gnu and cross-tested on aarch64-none-elf with no issues. OK? Thanks, James --- gcc/ 2015-12-04 James Greenhalgh * config/aarch64/aarch64.md (add3_pluslong): Add register constraints. gcc/testsuite/ 2015-12-04 James Greenhalgh * gcc.c-torture/compile/20151204.c: New. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 765df6a..79d1414 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1613,9 +1613,9 @@ (define_insn_and_split "*add3_pluslong" [(set - (match_operand:GPI 0 "register_operand" "") - (plus:GPI (match_operand:GPI 1 "register_operand" "") - (match_operand:GPI 2 "aarch64_pluslong_operand" "")))] + (match_operand:GPI 0 "register_operand" "=r") + (plus:GPI (match_operand:GPI 1 "register_operand" "r") + (match_operand:GPI 2 "aarch64_pluslong_immediate" "i")))] "!aarch64_plus_operand (operands[2], VOIDmode) && !aarch64_move_imm (INTVAL (operands[2]), mode)" "#" diff --git a/gcc/testsuite/gcc.c-torture/compile/20151204.c b/gcc/testsuite/gcc.c-torture/compile/20151204.c new file mode 100644 index 0000000..4a05671 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/compile/20151204.c @@ -0,0 +1,19 @@ +typedef __SIZE_TYPE__ size_t; + +int strcmp (const char*, const char*); +void *memchr (const void *, int, size_t); +char* strncpy (char *, const char *, size_t); + +int +main(int argc, char** argv) +{ + char target[32753] = "A"; + char buffer[32753]; + char *x; + x = buffer; + + if (strcmp (target, "A") + || memchr (target, 'A', 0) != ((void *) 0)) + if (strncpy (x, "", 4) != x); + return 0; +}