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[209.132.180.131]) by mx.google.com with ESMTPS id 14si17209630pfu.95.2016.11.04.08.48.49 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Nov 2016 08:48:49 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-440461-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-440461-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-440461-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; q=dns; s=default; b=lXuJSEEkeevF KlTrfa/re+7n8U7cUckcNCsezs1LF1Qc0ZHrEBK7b/PQ6dRJqeyO9sxIPH0QqqJ2 1hURUHEX4UvRBRXahld1lk4vSjl2+gt57YXpXe8VPMP+g4ByyBX1A8hn0m8dlSkS jF2i8dA5JdIJc1U9CXk8s0lNd1qJbMg= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; s=default; bh=DMpRkmF9pYZX5erb0N LqtghQV4U=; b=V7+fq1ILKlI0l0lIwU/Z9Gxh6e+L2+y81xqzDh+Hx38R8N8Q3z 0T3hdFBGayusHDd4PvChg5BHHdKX11ShuoC0UbRWox7ka5qq3VQMLHWrKMHoV0JN 73FCJQUovDbQXmMHHIwpBH1SX9jLWYk/naOOcWja8XQroXi7EFjqQXLe4= Received: (qmail 102709 invoked by alias); 4 Nov 2016 15:48:30 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 102695 invoked by uid 89); 4 Nov 2016 15:48:29 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=upcoming X-HELO: mail-pf0-f174.google.com Received: from mail-pf0-f174.google.com (HELO mail-pf0-f174.google.com) (209.85.192.174) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 04 Nov 2016 15:48:19 +0000 Received: by mail-pf0-f174.google.com with SMTP id n85so53902026pfi.1 for ; Fri, 04 Nov 2016 08:48:19 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=hsCQ6KCNE/65ardBt4ouN1r0ogoALpMmWTLxj5OSG5E=; b=mszizUxrduewhV/ND039h002InDAPv/cw+eiIsUNyQW3QjSdOcG3nMlvRvwtCvkaYz 3EUftWHk7QgFNY1AWHKVsvy8x3uKdwu/GXvIGNFWB07JNo085ZL2j2LXTcAE5eG2guDh qq0CpVbUZgGX/Zn/Wt2m1wK7i+UU9iqbJcfGendt6932WQ+OHRJJYwfmyqBPJyxnAvlQ 7Qx5UF/pKvDdRStUoB/jlBnGO9WLcV36XY8V2AuuOMl/E9GMBQbyjgMlnpMvNyEn3Wu5 +mN0/0grgRGTsw0H6ORJ3MH8QEyGPhwDv83/rXDj6U7hKThKgVLp4Dp4U7YhMDic+vnC H4mw== X-Gm-Message-State: ABUngvft59mYXzWjjJxUXsgnVbc4XQsa0N31dJFYyR40tHEngRW5ONiEQcMzPZn5XsJAfm8w X-Received: by 10.98.20.131 with SMTP id 125mr27699071pfu.51.1478274497685; Fri, 04 Nov 2016 08:48:17 -0700 (PDT) Received: from linaro-laptop.intra.reserved-bit.com ([124.248.185.144]) by smtp.gmail.com with ESMTPSA id u1sm21352891pfb.96.2016.11.04.08.48.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Nov 2016 08:48:16 -0700 (PDT) From: Siddhesh Poyarekar To: gcc-patches@gcc.gnu.org Cc: jim.wilson@linaro.org, Siddhesh Poyarekar Subject: [PATCH v2] Add mcpu flag for Qualcomm falkor core Date: Fri, 4 Nov 2016 22:47:54 +0700 Message-Id: <1478274474-8902-1-git-send-email-siddhesh.poyarekar@linaro.org> This adds an mcpu option for the upcoming Qualcomm Falkor core. This is identical to the qdf24xx part that was added earlier and hence retains the same tuning structure and continues to have the a57 pipeline for now. The part number has also been changed and this patch fixes this for both qdf24xx and falkor options. Tested with aarch64 and armhf. Siddhesh * gcc/config/aarch64/aarch64-cores.def (qdf24xx): Update part number. (falkor): New core. * gcc/config/aarch64/aarch64-tune.md: Regenerated. * gcc/config/arm/arm-cores.def (falkor): New core. * gcc/config/arm/arm-tables.opt: Regenerated. * gcc/config/arm/arm-tune.md: Regenerated. * gcc/config/arm/bpabi.h (BE8_LINK_SPEC): Add falkor support. * gcc/config/arm/t-aprofile (MULTILIB_MATCHES): Add falkor support. * gcc/doc/invoke.texi (AArch64 Options/-mtune): Add falkor. (ARM Options/-mtune): Add falkor. --- gcc/config/aarch64/aarch64-cores.def | 3 ++- gcc/config/aarch64/aarch64-tune.md | 2 +- gcc/config/arm/arm-cores.def | 1 + gcc/config/arm/arm-tables.opt | 3 +++ gcc/config/arm/arm-tune.md | 2 +- gcc/config/arm/bpabi.h | 2 ++ gcc/config/arm/t-aprofile | 1 + gcc/doc/invoke.texi | 9 +++++---- 8 files changed, 16 insertions(+), 7 deletions(-) -- 2.7.4 diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def index f9b7552..4b00f3f 100644 --- a/gcc/config/aarch64/aarch64-cores.def +++ b/gcc/config/aarch64/aarch64-cores.def @@ -54,7 +54,8 @@ AARCH64_CORE("cortex-a73", cortexa73, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AA AARCH64_CORE("exynos-m1", exynosm1, exynosm1, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, exynosm1, 0x53, 0x001) /* Qualcomm ('Q') cores. */ -AARCH64_CORE("qdf24xx", qdf24xx, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, qdf24xx, 0x51, 0x800) +AARCH64_CORE("falkor", falkor, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, qdf24xx, 0x51, 0xC00) +AARCH64_CORE("qdf24xx", qdf24xx, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, qdf24xx, 0x51, 0xC00) /* Cavium ('C') cores. */ AARCH64_CORE("thunderx", thunderx, thunderx, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx, 0x43, 0x0a1) diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md index 022b131..29afcdf 100644 --- a/gcc/config/aarch64/aarch64-tune.md +++ b/gcc/config/aarch64/aarch64-tune.md @@ -1,5 +1,5 @@ ;; -*- buffer-read-only: t -*- ;; Generated automatically by gentune.sh from aarch64-cores.def (define_attr "tune" - "cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,exynosm1,qdf24xx,thunderx,xgene1,vulcan,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53" + "cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,exynosm1,falkor,qdf24xx,thunderx,xgene1,vulcan,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53" (const (symbol_ref "((enum attr_tune) aarch64_tune)"))) diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def index 2072e1e..1bfec9c 100644 --- a/gcc/config/arm/arm-cores.def +++ b/gcc/config/arm/arm-cores.def @@ -173,6 +173,7 @@ ARM_CORE("cortex-a57", cortexa57, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED ARM_CORE("cortex-a72", cortexa72, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57) ARM_CORE("cortex-a73", cortexa73, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a73) ARM_CORE("exynos-m1", exynosm1, exynosm1, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), exynosm1) +ARM_CORE("falkor", falkor, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), qdf24xx) ARM_CORE("qdf24xx", qdf24xx, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), qdf24xx) ARM_CORE("xgene1", xgene1, xgene1, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH8A), xgene1) diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index ee9e3bb..7b15c8c 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -328,6 +328,9 @@ EnumValue Enum(processor_type) String(exynos-m1) Value(exynosm1) EnumValue +Enum(processor_type) String(falkor) Value(falkor) + +EnumValue Enum(processor_type) String(qdf24xx) Value(qdf24xx) EnumValue diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md index 594ce9d..867da26 100644 --- a/gcc/config/arm/arm-tune.md +++ b/gcc/config/arm/arm-tune.md @@ -34,7 +34,7 @@ cortexm3,marvell_pj4,cortexa15cortexa7, cortexa17cortexa7,cortexa32,cortexa35, cortexa53,cortexa57,cortexa72, - cortexa73,exynosm1,qdf24xx, + cortexa73,exynosm1,falkor,qdf24xx, xgene1,cortexa57cortexa53,cortexa72cortexa53, cortexa73cortexa35,cortexa73cortexa53" (const (symbol_ref "((enum attr_tune) arm_tune)"))) diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h index 0da98fb..dd4f122 100644 --- a/gcc/config/arm/bpabi.h +++ b/gcc/config/arm/bpabi.h @@ -79,6 +79,7 @@ |mcpu=cortex-a73.cortex-a35 \ |mcpu=cortex-a73.cortex-a53 \ |mcpu=exynos-m1 \ + |mcpu=falkor \ |mcpu=qdf24xx \ |mcpu=xgene1 \ |mcpu=cortex-m1.small-multiply \ @@ -117,6 +118,7 @@ |mcpu=cortex-a73.cortex-a35 \ |mcpu=cortex-a73.cortex-a53 \ |mcpu=exynos-m1 \ + |mcpu=falkor \ |mcpu=qdf24xx \ |mcpu=xgene1 \ |mcpu=cortex-m1.small-multiply \ diff --git a/gcc/config/arm/t-aprofile b/gcc/config/arm/t-aprofile index f852ecd..8b591ba 100644 --- a/gcc/config/arm/t-aprofile +++ b/gcc/config/arm/t-aprofile @@ -92,6 +92,7 @@ MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a73 MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a73.cortex-a35 MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a73.cortex-a53 MULTILIB_MATCHES += march?armv8-a=mcpu?exynos-m1 +MULTILIB_MATCHES += march?armv8-a=mcpu?falkor MULTILIB_MATCHES += march?armv8-a=mcpu?qdf24xx MULTILIB_MATCHES += march?armv8-a=mcpu?xgene1 diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index ad9304f..e3998d6 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -13845,10 +13845,10 @@ processors implementing the target architecture. Specify the name of the target processor for which GCC should tune the performance of the code. Permissible values for this option are: @samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57}, -@samp{cortex-a72}, @samp{cortex-a73}, @samp{exynos-m1}, @samp{qdf24xx}, -@samp{thunderx}, @samp{xgene1}, @samp{vulcan}, @samp{cortex-a57.cortex-a53}, -@samp{cortex-a72.cortex-a53}, @samp{cortex-a73.cortex-a35}, -@samp{cortex-a73.cortex-a53}, @samp{native}. +@samp{cortex-a72}, @samp{cortex-a73}, @samp{exynos-m1}, @samp{falkor}, +@samp{qdf24xx}, @samp{thunderx}, @samp{xgene1}, @samp{vulcan}, +@samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53}, +@samp{cortex-a73.cortex-a35}, @samp{cortex-a73.cortex-a53}, @samp{native}. The values @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53}, @samp{cortex-a73.cortex-a35}, @samp{cortex-a73.cortex-a53} @@ -14935,6 +14935,7 @@ Permissible names are: @samp{arm2}, @samp{arm250}, @samp{cortex-m0.small-multiply}, @samp{cortex-m0plus.small-multiply}, @samp{exynos-m1}, +@samp{falkor}, @samp{qdf24xx}, @samp{marvell-pj4}, @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312},