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[209.132.180.131]) by mx.google.com with ESMTPS id g189-v6si26189873pgc.204.2018.10.11.06.39.55 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Oct 2018 06:39:56 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-487343-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=NrneeUMy; spf=pass (google.com: domain of gcc-patches-return-487343-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-487343-patch=linaro.org@gcc.gnu.org" DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; q=dns; s= default; b=nERyso/3FEBPhQP9CoqUhsluXclvVmbvKI38B6dA9JRshtv0WwtyF E6vixA47hk1VnpXwjhsdrYmKWAx/2EOpN6rGPAOYetraqyFOZNFJSz1fsBdOMsw6 /Rbl88Zy41q5Mhy61eB1SfJ2YxWyRpucPZ/vU89JAwioNfV6fTJ5rU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; s=default; bh=skpw90Kj13TKTVY8oY2lh8DH/JU=; b=NrneeUMyvXv0kspzyOxDijLaYdXc NZk2D9LArv85kjsVoKDL/ff8FK7wabQrMoLj/WQvgbCFDS4AQaBUeFZpGSoy2S+h YVP6d2BNjAF6IoAW+tNBQc6lCWb8qrgNVcdDqcakmNgbkclQ8yn19fBTR4Pw87cc rfQWw2ldve5Y3xk= Received: (qmail 34471 invoked by alias); 11 Oct 2018 13:39:42 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 33197 invoked by uid 89); 11 Oct 2018 13:39:39 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-27.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 spammy=Hx-languages-length:2362 X-HELO: mx07-00178001.pphosted.com Received: from mx08-00178001.pphosted.com (HELO mx07-00178001.pphosted.com) (91.207.212.93) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 11 Oct 2018 13:39:37 +0000 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w9BDUF4g017795; Thu, 11 Oct 2018 15:39:35 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2n0muy76ep-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 11 Oct 2018 15:39:35 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id BD86F34; Thu, 11 Oct 2018 13:39:34 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag5node1.st.com [10.75.127.13]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id AA85F554F; Thu, 11 Oct 2018 13:39:34 +0000 (GMT) Received: from gnb.st.com (10.75.127.45) by SFHDAG5NODE1.st.com (10.75.127.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 11 Oct 2018 15:39:34 +0200 From: Christophe Lyon To: CC: Subject: [ARM/FDPIC v3 12/21] [ARM] FDPIC: Restore r9 after we call __aeabi_read_tp Date: Thu, 11 Oct 2018 15:34:49 +0200 Message-ID: <20181011133518.17258-13-christophe.lyon@st.com> In-Reply-To: <20181011133518.17258-1-christophe.lyon@st.com> References: <20181011133518.17258-1-christophe.lyon@st.com> MIME-Version: 1.0 X-IsSubscribed: yes We call __aeabi_read_tp() to get the thread pointer. Since this is a function call, we have to restore the FDPIC register afterwards. 2018-XX-XX Christophe Lyon Mickaël Guêné gcc/ * config/arm/arm.c (arm_load_tp): Add FDPIC support. * config/arm/arm.md (load_tp_soft_fdpic): New pattern. (load_tp_soft): Disable in FDPIC mode. Change-Id: I0a2e3466c9afb869ad8e844083ad178de014658e -- 2.6.3 diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index d7b7d99..d3a60cb 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -8646,7 +8646,25 @@ arm_load_tp (rtx target) rtx tmp; - emit_insn (gen_load_tp_soft ()); + if (TARGET_FDPIC) + { + rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (3)); + + emit_insn (gen_load_tp_soft_fdpic ()); + + /* Restore r9. */ + XVECEXP (par, 0, 0) + = gen_rtx_UNSPEC (VOIDmode, + gen_rtvec (2, gen_rtx_REG (Pmode, FDPIC_REGNUM), + get_hard_reg_initial_val (Pmode, FDPIC_REGNUM)), + UNSPEC_PIC_RESTORE); + XVECEXP (par, 0, 1) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, FDPIC_REGNUM)); + XVECEXP (par, 0, 2) + = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, FDPIC_REGNUM)); + emit_insn (par); + } + else + emit_insn (gen_load_tp_soft ()); tmp = gen_rtx_REG (SImode, R0_REGNUM); emit_move_insn (target, tmp); diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 09a0701..6fea087 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -11485,12 +11485,25 @@ ) ;; Doesn't clobber R1-R3. Must use r0 for the first operand. +(define_insn "load_tp_soft_fdpic" + [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS)) + (clobber (reg:SI 9)) + (clobber (reg:SI LR_REGNUM)) + (clobber (reg:SI IP_REGNUM)) + (clobber (reg:CC CC_REGNUM))] + "TARGET_SOFT_TP && TARGET_FDPIC" + "bl\\t__aeabi_read_tp\\t@ load_tp_soft" + [(set_attr "conds" "clob") + (set_attr "type" "branch")] +) + +;; Doesn't clobber R1-R3. Must use r0 for the first operand. (define_insn "load_tp_soft" [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS)) (clobber (reg:SI LR_REGNUM)) (clobber (reg:SI IP_REGNUM)) (clobber (reg:CC CC_REGNUM))] - "TARGET_SOFT_TP" + "TARGET_SOFT_TP && !TARGET_FDPIC" "bl\\t__aeabi_read_tp\\t@ load_tp_soft" [(set_attr "conds" "clob") (set_attr "type" "branch")]