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[209.132.180.131]) by mx.google.com with ESMTPS id w34si4486885edc.252.2019.10.18.12.59.21 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 18 Oct 2019 12:59:21 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-511331-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b="REs/G/UP"; spf=pass (google.com: domain of gcc-patches-return-511331-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-511331-patch=linaro.org@gcc.gnu.org" DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; q=dns; s=default; b=QU6E/d5gmPRHWK6G 4Zkzj5z7p4Vx+VuHeiBMbfXoytTAxDeoolesf/KUtErR5DQWt5QjqN7VHFRq2ymC FEni/jqg5H5AIfDujXT+smdNmOPIsond/Og8C0DAPUDLJ6IeNvCkEuJ/lOflXk09 RZwThvXgRe2q8XFevE6JhgwPjcs= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=default; bh=/Hn6m9pl2fXfQXDMrmUcZ+ XCxuk=; b=REs/G/UPQtJjU4UixdVY6ghB2kUI4GqbaKnhgP+gJ9QoyFmUKNXm6j a8Wg0oJpz07C5xk3B7EuoBa4tqIj8f0mvld6tVTbWqSVbM2AIJpLF/q0zmDW5haQ /W+P0aQBcigx1G2MIO1uz27RNcPHuIh4ujFNj+PWnCaIANK9hyY9E= Received: (qmail 115730 invoked by alias); 18 Oct 2019 19:55:50 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 114946 invoked by uid 89); 18 Oct 2019 19:55:44 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-19.1 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_FAIL autolearn=ham version=3.3.1 spammy= X-HELO: eggs.gnu.org Received: from eggs.gnu.org (HELO eggs.gnu.org) (209.51.188.92) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 18 Oct 2019 19:55:43 +0000 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iLYLd-0005BT-Q5 for gcc-patches@gcc.gnu.org; Fri, 18 Oct 2019 15:55:42 -0400 Received: from [217.140.110.172] (port=42782 helo=foss.arm.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1iLYLd-00056C-HP for gcc-patches@gcc.gnu.org; Fri, 18 Oct 2019 15:55:41 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8CA231762; Fri, 18 Oct 2019 12:49:27 -0700 (PDT) Received: from eagle.buzzard.freeserve.co.uk (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 19F613F6C4; Fri, 18 Oct 2019 12:49:26 -0700 (PDT) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [PATCH 22/29] [arm] Allow the summation result of signed add-with-overflow to be discarded. Date: Fri, 18 Oct 2019 20:48:53 +0100 Message-Id: <20191018194900.34795-23-Richard.Earnshaw@arm.com> In-Reply-To: <20191018194900.34795-1-Richard.Earnshaw@arm.com> References: <20191018194900.34795-1-Richard.Earnshaw@arm.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.110.172 This patch matches the signed add-with-overflow patterns when the summation itself is dropped. In this case we can use CMN (or CMP with some immediates). There are a small number of constants in thumb2 where this can result in less dense code (as we lack 16-bit CMN with immediate patterns). To handle this we use peepholes to try these alternatives when either a scratch is available (0 <= i <= 7) or the original register is dead (0 <= i <= 255). We don't use a scratch in the pattern as if those conditions are not satisfied then the 32-bit form is preferable to forcing a reload. * config/arm/arm.md (addsi3_compareV_reg_nosum): New insn. (addsi3_compareV_imm_nosum): New insn. Also add peephole2 patterns to transform this back into the summation version when that leads to smaller code. --- gcc/config/arm/arm.md | 78 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index b5214c79c35..be002f77382 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -803,6 +803,21 @@ (define_insn "addsi3_compareV_reg" (set_attr "type" "alus_sreg")] ) +(define_insn "*addsi3_compareV_reg_nosum" + [(set (reg:CC_V CC_REGNUM) + (compare:CC_V + (plus:DI + (sign_extend:DI (match_operand:SI 0 "register_operand" "%l,r")) + (sign_extend:DI (match_operand:SI 1 "register_operand" "l,r"))) + (sign_extend:DI (plus:SI (match_dup 0) (match_dup 1)))))] + "TARGET_32BIT" + "cmn%?\\t%0, %1" + [(set_attr "conds" "set") + (set_attr "arch" "t2,*") + (set_attr "length" "2,4") + (set_attr "type" "alus_sreg")] +) + (define_insn "addsi3_compareV_imm" [(set (reg:CC_V CC_REGNUM) (compare:CC_V @@ -828,6 +843,69 @@ (define_insn "addsi3_compareV_imm" (set_attr "type" "alus_imm")] ) +(define_insn "addsi3_compareV_imm_nosum" + [(set (reg:CC_V CC_REGNUM) + (compare:CC_V + (plus:DI + (sign_extend:DI + (match_operand:SI 0 "register_operand" "l,r,r")) + (match_operand 1 "arm_addimm_operand" "Pw,I,L")) + (sign_extend:DI (plus:SI (match_dup 0) (match_dup 1)))))] + "TARGET_32BIT + && INTVAL (operands[1]) == ARM_SIGN_EXTEND (INTVAL (operands[1]))" + "@ + cmp%?\\t%0, #%n1 + cmn%?\\t%0, %1 + cmp%?\\t%0, #%n1" + [(set_attr "conds" "set") + (set_attr "arch" "t2,*,*") + (set_attr "length" "2,4,4") + (set_attr "type" "alus_imm")] +) + +;; We can handle more constants efficently if we can clobber either a scratch +;; or the other source operand. We deliberately leave this late as in +;; high register pressure situations it's not worth forcing any reloads. +(define_peephole2 + [(match_scratch:SI 2 "l") + (set (reg:CC_V CC_REGNUM) + (compare:CC_V + (plus:DI + (sign_extend:DI + (match_operand:SI 0 "low_register_operand")) + (match_operand 1 "const_int_operand")) + (sign_extend:DI (plus:SI (match_dup 0) (match_dup 1)))))] + "TARGET_THUMB2 + && satisfies_constraint_Pd (operands[1])" + [(parallel[ + (set (reg:CC_V CC_REGNUM) + (compare:CC_V + (plus:DI (sign_extend:DI (match_dup 0)) + (sign_extend:DI (match_dup 1))) + (sign_extend:DI (plus:SI (match_dup 0) (match_dup 1))))) + (set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1)))])] +) + +(define_peephole2 + [(set (reg:CC_V CC_REGNUM) + (compare:CC_V + (plus:DI + (sign_extend:DI + (match_operand:SI 0 "low_register_operand")) + (match_operand 1 "const_int_operand")) + (sign_extend:DI (plus:SI (match_dup 0) (match_dup 1)))))] + "TARGET_THUMB2 + && dead_or_set_p (peep2_next_insn (0), operands[0]) + && satisfies_constraint_Py (operands[1])" + [(parallel[ + (set (reg:CC_V CC_REGNUM) + (compare:CC_V + (plus:DI (sign_extend:DI (match_dup 0)) + (sign_extend:DI (match_dup 1))) + (sign_extend:DI (plus:SI (match_dup 0) (match_dup 1))))) + (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))])] +) + (define_insn "addsi3_compare0" [(set (reg:CC_NOOV CC_REGNUM) (compare:CC_NOOV