From patchwork Fri Oct 18 19:48:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Richard Earnshaw \(lists\)" X-Patchwork-Id: 176946 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp1287823ocf; Fri, 18 Oct 2019 12:50:32 -0700 (PDT) X-Google-Smtp-Source: APXvYqwd6T0lnpx3A65FLsjvEcb29fC4gJSj0iN4RXcHYOdg0tIsX57hfYF8k10AeK7W13hADjiA X-Received: by 2002:a17:906:95cc:: with SMTP id n12mr8676758ejy.111.1571428231604; Fri, 18 Oct 2019 12:50:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571428231; cv=none; d=google.com; s=arc-20160816; b=HMDbq90zbWNTErHtULnDbGil9UM7Ui692a10uCcoeT1npPlNYL1rTFgkcPADK/wbj5 HpKzbSrdc9gVr+uRdzGjuBSTW8igYlJVo4iMiw8ZEZCJBGg9aEtIpMXA+dUPqQX5Woch bqXB7e6l3RKMG6GUo90PQrlXwk//huQrXtTgREzfaxAcXMRGUUycmNcPFYcgwceO7XYe Wv/NXiw9KlLZMXytXPhgbYW3ysCOZGPoeOB/oc6vWzW3+d53tr4oUPj/lgfXalXkGqqz xmHskvkC762ilGZoZlp2aCMjJLoj8WSZ77uN2KJgWGyHxa50jdzbX5C2cqTMNAP7iMhe Jizg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:delivered-to:sender:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mailing-list:dkim-signature :domainkey-signature; bh=9gHi8REhUCV4gO0Azii6takmJY71CXjguDo5A+PmBDk=; b=OMvYDN0YnUkNhCJi9qJJaljbYM4px5+jNZjqt+mSoV7vbu1FNhv9dX+4vFKJLMExy/ xVPBN8vkAehbQewG4u7kS+T1RZpU/8icKQMXqO4vj5nk5mrEaR2+Al/uHXl/niwEPWTV 5ESN8W4h50Tm43oxLwkVlMapT7h/UV6d4vgwBMZ0mYdpqMK/GUibxAClhN39XWgSRrhJ SlpiWMc0AmrQ7OzVRMVtDhGg+tTo1mkFyNhcV19XqhUdR/bhrp/m0Juer4NUK5+NnZLU je82NNt4t8UNxVI4kOsB3XFu5fUNSBAXjNNamBrJmRQ3NWUWsfeXGMhyp/O0f0rU9Kbj sNBg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=Gc8H0Dqn; spf=pass (google.com: domain of gcc-patches-return-511312-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-511312-patch=linaro.org@gcc.gnu.org" Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id c19si4890017ede.360.2019.10.18.12.50.30 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 18 Oct 2019 12:50:31 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-511312-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=Gc8H0Dqn; spf=pass (google.com: domain of gcc-patches-return-511312-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-511312-patch=linaro.org@gcc.gnu.org" DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; q=dns; s=default; b=xRoFxUPRHxW7pCU3 +ifAfffk2+kiko12Ql4dUkl7/mo91dkbDOgszDP0liuFIoylBtPqdmZyBUtqG/Wu /sl7YdIGz5TTgDwxbKkKEG8EtwoA0VQqdd4/82fGV50qJcjgyZgGR136tsrl4OPf OeolkjpgSXFNj9OvCar8bcKKRY8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=default; bh=GzGSerWzvFOro+zqdLkBvM Kyw3I=; b=Gc8H0Dqn6j+63+/bvF5O4jU+a0c6kn262lJxXD3b25kz9gMupmJCzV TLVUXkMfAFyfhTnYZEsWMrkjzhyM6XNhI1IOyOqv/SYmSZqC8XsiCz/7/NvvH+3N MrFWTXe28GIZtklZu/6HnzYyuyppXAhOWNWzx6Cbygi+peVuelqxs= Received: (qmail 77908 invoked by alias); 18 Oct 2019 19:49:36 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 77577 invoked by uid 89); 18 Oct 2019 19:49:26 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-18.4 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3 autolearn=ham version=3.3.1 spammy= X-HELO: foss.arm.com Received: from Unknown (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 18 Oct 2019 19:49:23 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7B8D215BE; Fri, 18 Oct 2019 12:49:14 -0700 (PDT) Received: from eagle.buzzard.freeserve.co.uk (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 090E73F6C4; Fri, 18 Oct 2019 12:49:13 -0700 (PDT) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [PATCH 03/29] [arm] Early split zero- and sign-extension Date: Fri, 18 Oct 2019 20:48:34 +0100 Message-Id: <20191018194900.34795-4-Richard.Earnshaw@arm.com> In-Reply-To: <20191018194900.34795-1-Richard.Earnshaw@arm.com> References: <20191018194900.34795-1-Richard.Earnshaw@arm.com> MIME-Version: 1.0 This patch changes the insn patterns for zero- and sign-extend into define_expands that generate the appropriate word operations immediately. * config/arm/arm.md (zero_extenddi2): Convert to define_expand. (extenddi2): Likewise. --- gcc/config/arm/arm.md | 75 +++++++++++++++++++++++++++++++------------ 1 file changed, 54 insertions(+), 21 deletions(-) diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 5ba42a13430..4a7a64e6613 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -4196,31 +4196,64 @@ (define_expand "truncdfhf2" ;; Zero and sign extension instructions. -(define_insn "zero_extenddi2" - [(set (match_operand:DI 0 "s_register_operand" "=r,?r") - (zero_extend:DI (match_operand:QHSI 1 "" - "")))] +(define_expand "zero_extenddi2" + [(set (match_operand:DI 0 "s_register_operand" "") + (zero_extend:DI (match_operand:QHSI 1 "" "")))] "TARGET_32BIT " - "#" - [(set_attr "length" "4,8") - (set_attr "arch" "*,*") - (set_attr "ce_count" "2") - (set_attr "predicable" "yes") - (set_attr "type" "mov_reg,multiple")] + { + rtx res_lo, res_hi, op0_lo, op0_hi; + res_lo = gen_lowpart (SImode, operands[0]); + res_hi = gen_highpart (SImode, operands[0]); + if (can_create_pseudo_p ()) + { + op0_lo = mode == SImode ? operands[1] : gen_reg_rtx (SImode); + op0_hi = gen_reg_rtx (SImode); + } + else + { + op0_lo = mode == SImode ? operands[1] : res_lo; + op0_hi = res_hi; + } + if (mode != SImode) + emit_insn (gen_rtx_SET (op0_lo, + gen_rtx_ZERO_EXTEND (SImode, operands[1]))); + emit_insn (gen_movsi (op0_hi, const0_rtx)); + if (res_lo != op0_lo) + emit_move_insn (res_lo, op0_lo); + if (res_hi != op0_hi) + emit_move_insn (res_hi, op0_hi); + DONE; + } ) -(define_insn "extenddi2" - [(set (match_operand:DI 0 "s_register_operand" "=r,?r,?r") - (sign_extend:DI (match_operand:QHSI 1 "" - "")))] +(define_expand "extenddi2" + [(set (match_operand:DI 0 "s_register_operand" "") + (sign_extend:DI (match_operand:QHSI 1 "" "")))] "TARGET_32BIT " - "#" - [(set_attr "length" "4,8,8") - (set_attr "ce_count" "2") - (set_attr "shift" "1") - (set_attr "predicable" "yes") - (set_attr "arch" "*,a,t") - (set_attr "type" "mov_reg,multiple,multiple")] + { + rtx res_lo, res_hi, op0_lo, op0_hi; + res_lo = gen_lowpart (SImode, operands[0]); + res_hi = gen_highpart (SImode, operands[0]); + if (can_create_pseudo_p ()) + { + op0_lo = mode == SImode ? operands[1] : gen_reg_rtx (SImode); + op0_hi = gen_reg_rtx (SImode); + } + else + { + op0_lo = mode == SImode ? operands[1] : res_lo; + op0_hi = res_hi; + } + if (mode != SImode) + emit_insn (gen_rtx_SET (op0_lo, + gen_rtx_SIGN_EXTEND (SImode, operands[1]))); + emit_insn (gen_ashrsi3 (op0_hi, op0_lo, GEN_INT (31))); + if (res_lo != op0_lo) + emit_move_insn (res_lo, op0_lo); + if (res_hi != op0_hi) + emit_move_insn (res_hi, op0_hi); + DONE; + } ) ;; Splits for all extensions to DImode