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[213.99.162.212]) by smtp.gmail.com with ESMTPSA id 19sm8046565wrc.47.2019.11.08.02.54.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Nov 2019 02:54:31 -0800 (PST) From: Richard Henderson To: gcc-patches@gcc.gnu.org Cc: richard.earnshaw@arm.com, james.greenhalgh@arm.com, richard.sandiford@arm.com, marcus.shawcroft@arm.com, kyrylo.tkachov@arm.com Subject: [PATCH 6/6] aarch64: Add testsuite checks for asm-flag Date: Fri, 8 Nov 2019 11:54:08 +0100 Message-Id: <20191108105408.27584-7-richard.henderson@linaro.org> In-Reply-To: <20191108105408.27584-1-richard.henderson@linaro.org> References: <20191108105408.27584-1-richard.henderson@linaro.org> Inspired by the tests in gcc.target/i386. Testing code generation, diagnostics, and execution. * gcc.target/aarch64/asm-flag-1.c: New test. * gcc.target/aarch64/asm-flag-3.c: New test. * gcc.target/aarch64/asm-flag-5.c: New test. * gcc.target/aarch64/asm-flag-6.c: New test. --- gcc/testsuite/gcc.target/aarch64/asm-flag-1.c | 34 +++++++++++++++ gcc/testsuite/gcc.target/aarch64/asm-flag-3.c | 36 ++++++++++++++++ gcc/testsuite/gcc.target/aarch64/asm-flag-5.c | 30 +++++++++++++ gcc/testsuite/gcc.target/aarch64/asm-flag-6.c | 43 +++++++++++++++++++ 4 files changed, 143 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-5.c create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-6.c -- 2.17.1 diff --git a/gcc/testsuite/gcc.target/aarch64/asm-flag-1.c b/gcc/testsuite/gcc.target/aarch64/asm-flag-1.c new file mode 100644 index 00000000000..e3e79c29b8f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/asm-flag-1.c @@ -0,0 +1,34 @@ +/* Test the valid @cc asm flag outputs. */ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +#ifndef __GCC_ASM_FLAG_OUTPUTS__ +#error "missing preprocessor define" +#endif + +void f(char *out) +{ + asm("" + : "=@ccne"(out[0]), "=@cceq"(out[1]), + "=@cccs"(out[2]), "=@cccc"(out[3]), + "=@ccmi"(out[4]), "=@ccpl"(out[5]), + "=@ccvs"(out[6]), "=@ccvc"(out[7]), + "=@cchi"(out[8]), "=@ccls"(out[9]), + "=@ccge"(out[10]), "=@cclt"(out[11]), + "=@ccgt"(out[12]), "=@ccle"(out[13])); +} + +/* { dg-final { scan-assembler "cset.*, ne" } } */ +/* { dg-final { scan-assembler "cset.*, eq" } } */ +/* { dg-final { scan-assembler "cset.*, cs" } } */ +/* { dg-final { scan-assembler "cset.*, cc" } } */ +/* { dg-final { scan-assembler "cset.*, mi" } } */ +/* { dg-final { scan-assembler "cset.*, pl" } } */ +/* { dg-final { scan-assembler "cset.*, vs" } } */ +/* { dg-final { scan-assembler "cset.*, vc" } } */ +/* { dg-final { scan-assembler "cset.*, hi" } } */ +/* { dg-final { scan-assembler "cset.*, ls" } } */ +/* { dg-final { scan-assembler "cset.*, ge" } } */ +/* { dg-final { scan-assembler "cset.*, ls" } } */ +/* { dg-final { scan-assembler "cset.*, gt" } } */ +/* { dg-final { scan-assembler "cset.*, le" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/asm-flag-3.c b/gcc/testsuite/gcc.target/aarch64/asm-flag-3.c new file mode 100644 index 00000000000..8b0bd8a00f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/asm-flag-3.c @@ -0,0 +1,36 @@ +/* Test some of the valid @cc asm flag outputs. */ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +#define DO(C) \ +void f##C(void) { char x; asm("" : "=@cc"#C(x)); if (!x) asm(""); asm(""); } + +DO(ne) +DO(eq) +DO(cs) +DO(cc) +DO(mi) +DO(pl) +DO(vs) +DO(vc) +DO(hi) +DO(ls) +DO(ge) +DO(lt) +DO(gt) +DO(le) + +/* { dg-final { scan-assembler "bne" } } */ +/* { dg-final { scan-assembler "beq" } } */ +/* { dg-final { scan-assembler "bcs" } } */ +/* { dg-final { scan-assembler "bcc" } } */ +/* { dg-final { scan-assembler "bmi" } } */ +/* { dg-final { scan-assembler "bpl" } } */ +/* { dg-final { scan-assembler "bvs" } } */ +/* { dg-final { scan-assembler "bvc" } } */ +/* { dg-final { scan-assembler "bhi" } } */ +/* { dg-final { scan-assembler "bls" } } */ +/* { dg-final { scan-assembler "bge" } } */ +/* { dg-final { scan-assembler "blt" } } */ +/* { dg-final { scan-assembler "bgt" } } */ +/* { dg-final { scan-assembler "ble" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/asm-flag-5.c b/gcc/testsuite/gcc.target/aarch64/asm-flag-5.c new file mode 100644 index 00000000000..4d4394e1478 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/asm-flag-5.c @@ -0,0 +1,30 @@ +/* Test error conditions of asm flag outputs. */ +/* { dg-do compile } */ +/* { dg-options "" } */ + +void f_B(void) { _Bool x; asm("" : "=@cccc"(x)); } +void f_c(void) { char x; asm("" : "=@cccc"(x)); } +void f_s(void) { short x; asm("" : "=@cccc"(x)); } +void f_i(void) { int x; asm("" : "=@cccc"(x)); } +void f_l(void) { long x; asm("" : "=@cccc"(x)); } +void f_ll(void) { long long x; asm("" : "=@cccc"(x)); } + +void f_f(void) +{ + float x; + asm("" : "=@cccc"(x)); /* { dg-error invalid type } */ +} + +void f_d(void) +{ + double x; + asm("" : "=@cccc"(x)); /* { dg-error invalid type } */ +} + +struct S { int x[3]; }; + +void f_S(void) +{ + struct S x; + asm("" : "=@cccc"(x)); /* { dg-error invalid type } */ +} diff --git a/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c b/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c new file mode 100644 index 00000000000..d9b90b8e517 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c @@ -0,0 +1,43 @@ +/* Executable testcase for 'output flags.' */ +/* { dg-do run } */ + +int test_bits (long nzcv) +{ + long n, z, c, v; + + __asm__ ("msr nzcv, %[in]" + : "=@ccmi"(n), "=@cceq"(z), "=@cccs"(c), "=@ccvs"(v) + : [in] "r"(nzcv << 28)); + + return n * 8 + z * 4 + c * 2 + v == nzcv; +} + +int test_cmp (long x, long y) +{ + long gt, lt, ge, le; + + __asm__ ("cmp %[x], %[y]" + : "=@ccgt"(gt), "=@cclt"(lt), "=@ccge"(ge), "=@ccle"(le) + : [x] "r"(x), [y] "r"(y)); + + return (gt == (x > y) + && lt == (x < y) + && ge == (x >= y) + && le == (x <= y)); +} + +int main () +{ + long i, j; + + for (i = 0; i < 16; ++i) + if (!test_bits (i)) + __builtin_abort (); + + for (i = -1; i <= 1; ++i) + for (j = -1; j <= 1; ++j) + if (!test_cmp (i, j)) + __builtin_abort (); + + return 0; +}