From patchwork Thu Oct 26 20:37:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neal Frager X-Patchwork-Id: 738339 Delivered-To: patch@linaro.org Received: by 2002:a5d:5101:0:b0:32d:baff:b0ca with SMTP id s1csp84281wrt; Thu, 26 Oct 2023 13:37:40 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG2pBm5gcl8qLKf3MU813qk2sBQhNKjHBUhFZjMNlrr3jH9yZ4MOi9p28WEWTmsJEtiHjDw X-Received: by 2002:ad4:5b87:0:b0:65d:660:25a8 with SMTP id 7-20020ad45b87000000b0065d066025a8mr854560qvp.20.1698352660699; Thu, 26 Oct 2023 13:37:40 -0700 (PDT) ARC-Seal: i=3; a=rsa-sha256; t=1698352660; cv=pass; d=google.com; s=arc-20160816; b=iqTv4ViOX7Vk2rDk9g/HGSnllLViQAO5FFhfYusuFYYw2GQ3VnkvN2lzkhLETvxWdo iNY0BRUaSAKMg/a/WtiRtwJ3MvDSfrFoOVaHFAYqWjB7dJR6u55xY6swu4TLW5ml8c6L 0eNeHVM7D9rgj0QNqrdMGF3tuG02El26R/gfmz7s1Vw1KcEuRYAKQaB8mOFfa5e/69nH JfyqB84RCgsQU4RAfhQyc72TVlWu6pAfcJWrcfhBXs5Kc8c4n8gCy1EdV27sOAZ+itFJ McaHPhP0OpgeyGfdR7TGIw9vezTzNnym4cBkcrV5XAAXBXQHpzYlMj/e5PVMx3uQ3fi5 9gNA== ARC-Message-Signature: i=3; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:message-id:date:subject:cc:to:from:dkim-signature :arc-filter:dmarc-filter:delivered-to; bh=KCUE0SW2q7Pw/RUOxPVx/SR7o9zAQ87uP8M6iWvIzpg=; fh=yRADZcmw/G6ekBwW/4lHPdEw06SO4uLMmcVaZMeeVeM=; b=kz+QXH49Rw3x++l14501xAGMNIEByxnPSEPxM72G4asL/dvqAOtwMr7uTqzuNKShvH 2W3DcOQNhJqAxV4WbYi0++Iazw8LTFJRBIgN1cDlqd5brnSIpfU8E5hlkVMcAideDVgu MWsEEt85uwG5Oa7nlM/XF0deWNczSSoqKnmw4LRuUqauEmAHDsiKY+4axHmsoIHAO6Jz X96YhpRgyVszoHbJEpxz1xWjExCmGc5M6nuxfS2Yenx+SXCo157APWpreRRUTEAd22rB ZMJmrP94FBRHYHYMRMT2xY52Dl1iDplH+E4QxD7tPdyDrnqsbrsSnyqyy0cYI9XlQl/s vP3g== ARC-Authentication-Results: i=3; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=UqpzdXk4; arc=pass (i=2); spf=pass (google.com: domain of gcc-patches-bounces+patch=linaro.org@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+patch=linaro.org@gcc.gnu.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Return-Path: Received: from server2.sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id pc3-20020a056214488300b0066dac72db9bsi127644qvb.346.2023.10.26.13.37.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Oct 2023 13:37:40 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+patch=linaro.org@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=UqpzdXk4; arc=pass (i=2); spf=pass (google.com: domain of gcc-patches-bounces+patch=linaro.org@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+patch=linaro.org@gcc.gnu.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5551B38555B9 for ; Thu, 26 Oct 2023 20:37:40 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2069.outbound.protection.outlook.com [40.107.220.69]) by sourceware.org (Postfix) with ESMTPS id 48ABD385840F for ; Thu, 26 Oct 2023 20:37:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 48ABD385840F Authentication-Results: sourceware.org; dmarc=fail (p=quarantine dis=none) header.from=amd.com Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=amd.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 48ABD385840F Authentication-Results: server2.sourceware.org; arc=pass smtp.remote-ip=40.107.220.69 ARC-Seal: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1698352654; cv=pass; b=bx1qMGghfKhsWFXxXuT9SmbnTH3QqrvcSGu5e9aWTuZNnyP0LcJYtv4YmZkuXrbxOwqaKnQlSALVBrTrnq22J4fARRp30fPT4nE8VdJNk8OubEF1It8RZDYbydNGx0Cf7rJj7e64GquDy9B8uMwZs+EPZ4mdFU/NMcrLl7NTnlc= ARC-Message-Signature: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1698352654; c=relaxed/simple; bh=HLq+x0uq/UCByIE3J3CFwNna/VIV8ZAvcCoFrIhr8w4=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=emdk40SJyYTe8jhhWhzyHvoT2ZRAENIHYsE9+vqhmc0eizN+MU+M1lt7P7+JE3J3Af8uAY0IqilZB6iPHqVkOUuPlwjMoDyvLxTMAnMsWxf5XQ+Hve9C6T84FGeoJeGGuD2yyo0nDX8pH5x5rAUDlWRwiDUiKFK9Rox6a7FmJQc= ARC-Authentication-Results: i=2; server2.sourceware.org ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=GfUczAlDbyua7XeZMaaaHtseAr4ThrX8UCg9HQalOBqVc0SZKfph3YcCtCk933Ixi+JIGDIzrpoan7GvM4YTegZtybiY9YySoPRh9x2qleHcubZmpjujN4ZMeY/WJBWYuo1MtRu3lDpUB8QRmsqRf2duCd3xBGlijrzn5V4+d+U8DvAPBFSeofAyeb+B6zLWR3iR5NNwDJm/0xHNkS5TW0F0Ai4Yd6ecB10jYuCI2I0qR+hJZYbL6R9+CT+ymmKq1NBD6V3mzMeEPlpiNw9m2rRPvZ5DR2kMNsWIFxeTzxL6GRpmL1R74Vi7zaYpFIuvKeBjvCYwOS2riUum4YkWhg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=KCUE0SW2q7Pw/RUOxPVx/SR7o9zAQ87uP8M6iWvIzpg=; b=cwK3ck7ENrFj4tr3iDN72FAWKBfTydgHHmiFsALUwP0GXNK4dTG2YSULOlZM7kkvUPuSqUOkhZyrdVzO56J1c+n5jOpjMEowLi+8QB8v6CzuXbUamLDgg2UhpVleYgJ0ETTpWCk6covvzGDYvjc92Wm17yb/8J1mhipOKkvpI3B/IYLI+Rmdb3JGAwkcZsMosgJNp5cJ/9e+cZ31SuTR+ISuma/cfwGbJIUSIOVqtNJN9QvLLl2D/gES9dfzlpOuCoTH+wQ6/vcK0o94BV+2bJEfjwlRQo+EnsYGiyr96D1r1MTAZtvhLV3VmX1qsBdrYKt57aATZ9MSF7Mgb+3baw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=KCUE0SW2q7Pw/RUOxPVx/SR7o9zAQ87uP8M6iWvIzpg=; b=UqpzdXk4R9lxg1xEhtGJKTALL6t3u7qSVZQDuVl1mdynwcW4h4MK9Cqalca7g4td0w6a1R2UBC1H+40iYgSNZ0FQkIREdwlLsXTm2v+OqYGpdJ38upmhMCHILu+zzAfAQbAxDxH3q8qrZA00W+Df/yRzAJV0P/3Fsr1JYaYtVbk= Received: from MW4P221CA0006.NAMP221.PROD.OUTLOOK.COM (2603:10b6:303:8b::11) by BL3PR12MB6426.namprd12.prod.outlook.com (2603:10b6:208:3b5::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6907.33; Thu, 26 Oct 2023 20:37:29 +0000 Received: from MWH0EPF000989E6.namprd02.prod.outlook.com (2603:10b6:303:8b:cafe::b3) by MW4P221CA0006.outlook.office365.com (2603:10b6:303:8b::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6907.34 via Frontend Transport; Thu, 26 Oct 2023 20:37:28 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by MWH0EPF000989E6.mail.protection.outlook.com (10.167.241.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6933.15 via Frontend Transport; Thu, 26 Oct 2023 20:37:28 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Thu, 26 Oct 2023 15:37:26 -0500 Received: from xirengwts09.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.32 via Frontend Transport; Thu, 26 Oct 2023 15:37:25 -0500 From: Neal Frager To: , , CC: , , , , , , , Neal Frager Subject: [PATCH v4 1/1] gcc: config: microblaze: fix cpu version check Date: Thu, 26 Oct 2023 21:37:22 +0100 Message-ID: <20231026203722.3596212-1-neal.frager@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989E6:EE_|BL3PR12MB6426:EE_ X-MS-Office365-Filtering-Correlation-Id: 712bd6a4-d1e7-45b8-f16f-08dbd6635f29 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Vtq6F839DmjqS5HCRUd91NTjXO70ysJkxcGopx/MqKAsz1m46W8DemmMKEdh6XL5jQoKPBY34od3gBd+dXSS5HkqWpKykR7LKzffVF3aenZBawvowaGnwjM1j4DbkXhwmG8CzPvHKYqYdDr56v4iXJcXdVo6aRn8l/Oi6b8iRD2xlPO7SzlaxlfMnU5yU1y2pBiwW5QVhhqbDVhE2tfFnpGoSQs1qaQlqbAZcEGTgImC5uO8Q3/8r/BVZmBBEp8E4ZlQCVs1dfH/Tel1IPSZx5V9fC0hOKmvoADl7lcF6Z56w5cshiUxL2VRsJZ4hMddq6ZIKETX5PHKHpm0idW0wdPJClCUMXQPsLDbVS6rHVNns/YOtzlW3DRu/LATxTHK4gSyE7wo9B+vHeQRyknwE8LmOuVRrkIlF5iZpqmHi3KA00r7HODlnbn8IETpCYj6/s3LTp6/xTyfpykWbIXib23TYFz9uL7qy50fKQCPc6GqBEEMbknx6exfjWN/TyPHqdS4xKLX0F5GaqKFq+8BqgK9PN/09gB/zJn3JHTbqhLxQgBPn6/6An1F2xozqpvKACmbiv+VsyMjSzoKMiAaWGX/n6wzm2qITwxM2YUFVfWMrmauHIwZwufkGj1K4vhU5e37UZdKVbChxk87b9pVfhWYbHbf23PJzvjuPhyMd6+HJx4A+ZWOIA+XJ5svzBJ+PfM1+Yivr9+JjwL93xT7a2FiGINO/WXCzrHCAPy4VXDIzTGA8gJsrEkk8MA8oSzk1SijatD1VTP1Z15GnUvge059BTAyejYjvV+J25A66jg= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(4636009)(136003)(346002)(376002)(39860400002)(396003)(230922051799003)(186009)(82310400011)(1800799009)(451199024)(64100799003)(40470700004)(36840700001)(46966006)(83380400001)(40480700001)(8676002)(40460700003)(2906002)(1076003)(2616005)(86362001)(30864003)(478600001)(110136005)(316002)(54906003)(70206006)(8936002)(44832011)(41300700001)(4001150100001)(70586007)(4326008)(36756003)(6666004)(5660300002)(426003)(82740400003)(336012)(26005)(356005)(81166007)(36860700001)(47076005)(36900700001)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Oct 2023 20:37:28.8029 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 712bd6a4-d1e7-45b8-f16f-08dbd6635f29 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989E6.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6426 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FORGED_SPF_HELO, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patch=linaro.org@gcc.gnu.org The MICROBLAZE_VERSION_COMPARE was incorrectly using strcasecmp instead of strverscmp to check the mcpu version against feature options. By simply changing the define to use strverscmp, the new version 10.0 is treated correctly as a higher version than previous versions. Signed-off-by: Neal Frager --- V1->V2: - No need to create a new microblaze specific version check routine as strverscmp is the correct solution. V2->V3: - Changed mcpu define for microblaze isa testsuite examples. V3->V4: - Added ChangeLog --- gcc/ChangeLog | 4 ++++ gcc/config/microblaze/microblaze.cc | 2 +- gcc/testsuite/gcc.target/microblaze/isa/bshift.c | 2 +- gcc/testsuite/gcc.target/microblaze/isa/div.c | 2 +- gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c | 2 +- gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c | 2 +- gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c | 2 +- gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c | 2 +- gcc/testsuite/gcc.target/microblaze/isa/fcvt.c | 2 +- gcc/testsuite/gcc.target/microblaze/isa/float.c | 2 +- gcc/testsuite/gcc.target/microblaze/isa/fsqrt.c | 2 +- gcc/testsuite/gcc.target/microblaze/isa/mul-bshift-pcmp.c | 2 +- gcc/testsuite/gcc.target/microblaze/isa/mul-bshift.c | 2 +- gcc/testsuite/gcc.target/microblaze/isa/mul.c | 2 +- gcc/testsuite/gcc.target/microblaze/isa/mulh-bshift-pcmp.c | 2 +- gcc/testsuite/gcc.target/microblaze/isa/mulh.c | 2 +- gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c | 2 +- gcc/testsuite/gcc.target/microblaze/isa/nofloat.c | 2 +- gcc/testsuite/gcc.target/microblaze/isa/pcmp.c | 2 +- gcc/testsuite/gcc.target/microblaze/isa/vanilla.c | 2 +- gcc/testsuite/gcc.target/microblaze/microblaze.exp | 2 +- 21 files changed, 24 insertions(+), 20 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d50cd42a7d4..d5fee35bda4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2023-10-26 Neal Frager + + * config/microblaze/microblaze.cc: Fix mcpu version check. + 2023-10-25 Iain Sandoe * config/darwin.cc (darwin_override_options): Handle fPIE. diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc index c9f6c4198cf..60ad55120d2 100644 --- a/gcc/config/microblaze/microblaze.cc +++ b/gcc/config/microblaze/microblaze.cc @@ -56,7 +56,7 @@ /* This file should be included last. */ #include "target-def.h" -#define MICROBLAZE_VERSION_COMPARE(VA,VB) strcasecmp (VA, VB) +#define MICROBLAZE_VERSION_COMPARE(VA,VB) strverscmp (VA, VB) /* Classifies an address. diff --git a/gcc/testsuite/gcc.target/microblaze/isa/bshift.c b/gcc/testsuite/gcc.target/microblaze/isa/bshift.c index 64cf1e2e59e..664586bff9f 100644 --- a/gcc/testsuite/gcc.target/microblaze/isa/bshift.c +++ b/gcc/testsuite/gcc.target/microblaze/isa/bshift.c @@ -1,4 +1,4 @@ -/* { dg-options "-O3 -mcpu=v6.00.a -mxl-barrel-shift" } */ +/* { dg-options "-O3 -mcpu=v10.0 -mxl-barrel-shift" } */ volatile int m1, m2, m3; volatile unsigned int u1, u2, u3; diff --git a/gcc/testsuite/gcc.target/microblaze/isa/div.c b/gcc/testsuite/gcc.target/microblaze/isa/div.c index 25ee42ce5c8..783e7c0f684 100644 --- a/gcc/testsuite/gcc.target/microblaze/isa/div.c +++ b/gcc/testsuite/gcc.target/microblaze/isa/div.c @@ -1,4 +1,4 @@ -/* { dg-options "-O3 -mcpu=v6.00.a -mno-xl-soft-div" } */ +/* { dg-options "-O3 -mcpu=v10.0 -mno-xl-soft-div" } */ volatile int m1, m2, m3; volatile long l1, l2; diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c index 4041a241391..b6202e168d6 100644 --- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c +++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c @@ -1,4 +1,4 @@ -/* { dg-options "-O3 -mcpu=v6.00.a -mhard-float" } */ +/* { dg-options "-O3 -mcpu=v10.0 -mhard-float" } */ volatile float f1, f2, f3; diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c index 3902b839db9..4386c6e6cc3 100644 --- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c +++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c @@ -1,4 +1,4 @@ -/* { dg-options "-O3 -mcpu=v6.00.a -mhard-float" } */ +/* { dg-options "-O3 -mcpu=v10.0 -mhard-float" } */ volatile float f1, f2, f3; diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c index 8555974dda5..b414e48fe1b 100644 --- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c +++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c @@ -1,4 +1,4 @@ -/* { dg-options "-O3 -mcpu=v6.00.a -mhard-float" } */ +/* { dg-options "-O3 -mcpu=v10.0 -mhard-float" } */ volatile float f1, f2, f3; diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c index 79cc5f9dd8e..ff137012df4 100644 --- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c +++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c @@ -1,4 +1,4 @@ -/* { dg-options "-O3 -mcpu=v6.00.a -mhard-float" } */ +/* { dg-options "-O3 -mcpu=v10.0 -mhard-float" } */ void float_func(float f1, float f2, float f3) { diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcvt.c b/gcc/testsuite/gcc.target/microblaze/isa/fcvt.c index ee057c1b6ac..90fd45bd3b3 100644 --- a/gcc/testsuite/gcc.target/microblaze/isa/fcvt.c +++ b/gcc/testsuite/gcc.target/microblaze/isa/fcvt.c @@ -1,4 +1,4 @@ -/* { dg-options "-O3 -mcpu=v6.00.a -mhard-float -mxl-float-convert" } */ +/* { dg-options "-O3 -mcpu=v10.0 -mhard-float -mxl-float-convert" } */ int float_func (float f) { diff --git a/gcc/testsuite/gcc.target/microblaze/isa/float.c b/gcc/testsuite/gcc.target/microblaze/isa/float.c index f5ef3186cdd..212435d6435 100644 --- a/gcc/testsuite/gcc.target/microblaze/isa/float.c +++ b/gcc/testsuite/gcc.target/microblaze/isa/float.c @@ -1,4 +1,4 @@ -/* { dg-options "-O3 -mcpu=v6.00.a -mhard-float" } */ +/* { dg-options "-O3 -mcpu=v10.0 -mhard-float" } */ volatile float f1, f2, f3; diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fsqrt.c b/gcc/testsuite/gcc.target/microblaze/isa/fsqrt.c index 4c2466e4a55..834767d7a40 100644 --- a/gcc/testsuite/gcc.target/microblaze/isa/fsqrt.c +++ b/gcc/testsuite/gcc.target/microblaze/isa/fsqrt.c @@ -1,4 +1,4 @@ -/* { dg-options "-O3 -mcpu=v6.00.a -mhard-float -mxl-float-sqrt" } */ +/* { dg-options "-O3 -mcpu=v10.0 -mhard-float -mxl-float-sqrt" } */ #include float sqrt_func (float f) diff --git a/gcc/testsuite/gcc.target/microblaze/isa/mul-bshift-pcmp.c b/gcc/testsuite/gcc.target/microblaze/isa/mul-bshift-pcmp.c index ce186314e6a..2720ad38f57 100644 --- a/gcc/testsuite/gcc.target/microblaze/isa/mul-bshift-pcmp.c +++ b/gcc/testsuite/gcc.target/microblaze/isa/mul-bshift-pcmp.c @@ -1,4 +1,4 @@ -/* { dg-options "-O3 -mcpu=v6.00.a -mxl-barrel-shift -mno-xl-soft-mul -mxl-pattern-compare" } */ +/* { dg-options "-O3 -mcpu=v10.0 -mxl-barrel-shift -mno-xl-soft-mul -mxl-pattern-compare" } */ volatile int m1, m2, m3; volatile unsigned int u1, u2, u3; diff --git a/gcc/testsuite/gcc.target/microblaze/isa/mul-bshift.c b/gcc/testsuite/gcc.target/microblaze/isa/mul-bshift.c index 76d174ec7c3..59a17c79bbe 100644 --- a/gcc/testsuite/gcc.target/microblaze/isa/mul-bshift.c +++ b/gcc/testsuite/gcc.target/microblaze/isa/mul-bshift.c @@ -1,4 +1,4 @@ -/* { dg-options "-O3 -mcpu=v6.00.a -mxl-barrel-shift -mno-xl-soft-mul" } */ +/* { dg-options "-O3 -mcpu=v10.0 -mxl-barrel-shift -mno-xl-soft-mul" } */ volatile int m1, m2, m3; volatile unsigned int u1, u2, u3; diff --git a/gcc/testsuite/gcc.target/microblaze/isa/mul.c b/gcc/testsuite/gcc.target/microblaze/isa/mul.c index d2a6bec61e2..e4e330a0d0c 100644 --- a/gcc/testsuite/gcc.target/microblaze/isa/mul.c +++ b/gcc/testsuite/gcc.target/microblaze/isa/mul.c @@ -1,4 +1,4 @@ -/* { dg-options "-O3 -mcpu=v6.00.a -mno-xl-soft-mul" } */ +/* { dg-options "-O3 -mcpu=v10.0 -mno-xl-soft-mul" } */ volatile int m1, m2, m3; volatile long l1, l2; diff --git a/gcc/testsuite/gcc.target/microblaze/isa/mulh-bshift-pcmp.c b/gcc/testsuite/gcc.target/microblaze/isa/mulh-bshift-pcmp.c index a15983af117..0f962030fdd 100644 --- a/gcc/testsuite/gcc.target/microblaze/isa/mulh-bshift-pcmp.c +++ b/gcc/testsuite/gcc.target/microblaze/isa/mulh-bshift-pcmp.c @@ -1,4 +1,4 @@ -/* { dg-options "-O3 -mcpu=v6.00.a -mxl-barrel-shift -mno-xl-soft-mul -mxl-pattern-compare -mxl-multiply-high" } */ +/* { dg-options "-O3 -mcpu=v10.0 -mxl-barrel-shift -mno-xl-soft-mul -mxl-pattern-compare -mxl-multiply-high" } */ volatile int m1, m2, m3; volatile unsigned int u1, u2, u3; diff --git a/gcc/testsuite/gcc.target/microblaze/isa/mulh.c b/gcc/testsuite/gcc.target/microblaze/isa/mulh.c index 6e0cc3ac470..da28e8c4d1e 100644 --- a/gcc/testsuite/gcc.target/microblaze/isa/mulh.c +++ b/gcc/testsuite/gcc.target/microblaze/isa/mulh.c @@ -1,4 +1,4 @@ -/* { dg-options "-O3 -mcpu=v6.00.a -mno-xl-soft-mul -mxl-multiply-high" } */ +/* { dg-options "-O3 -mcpu=v10.0 -mno-xl-soft-mul -mxl-multiply-high" } */ volatile int m1, m2, m3; volatile unsigned int u1, u2, u3; diff --git a/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c b/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c index ebfb170ecee..86910fc347a 100644 --- a/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c +++ b/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c @@ -1,4 +1,4 @@ -/* { dg-options "-O3 -mcpu=v6.00.a " } */ +/* { dg-options "-O3 -mcpu=v10.0" } */ volatile float f1, f2, f3; diff --git a/gcc/testsuite/gcc.target/microblaze/isa/nofloat.c b/gcc/testsuite/gcc.target/microblaze/isa/nofloat.c index 647da3cfe24..b1f0268715d 100644 --- a/gcc/testsuite/gcc.target/microblaze/isa/nofloat.c +++ b/gcc/testsuite/gcc.target/microblaze/isa/nofloat.c @@ -1,4 +1,4 @@ -/* { dg-options "-O3 -mcpu=v6.00.a -msoft-float" } */ +/* { dg-options "-O3 -mcpu=v10.0 -msoft-float" } */ volatile float f1, f2, f3; diff --git a/gcc/testsuite/gcc.target/microblaze/isa/pcmp.c b/gcc/testsuite/gcc.target/microblaze/isa/pcmp.c index aea79572103..d9e5793f6f5 100644 --- a/gcc/testsuite/gcc.target/microblaze/isa/pcmp.c +++ b/gcc/testsuite/gcc.target/microblaze/isa/pcmp.c @@ -1,4 +1,4 @@ -/* { dg-options "-O3 -mcpu=v6.00.a -mxl-pattern-compare" } */ +/* { dg-options "-O3 -mcpu=v10.0 -mxl-pattern-compare" } */ volatile int m1, m2, m3; volatile long l1, l2; diff --git a/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c b/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c index 1d6ba807b12..35824b6d077 100644 --- a/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c +++ b/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c @@ -1,4 +1,4 @@ -/* { dg-options "-O3 -mcpu=v6.00.a -mcpu=v6.00.a" } */ +/* { dg-options "-O3 -mcpu=v10.0" } */ volatile int m1, m2, m3; volatile long l1, l2; diff --git a/gcc/testsuite/gcc.target/microblaze/microblaze.exp b/gcc/testsuite/gcc.target/microblaze/microblaze.exp index 1c7b0e23353..33979ae5e42 100644 --- a/gcc/testsuite/gcc.target/microblaze/microblaze.exp +++ b/gcc/testsuite/gcc.target/microblaze/microblaze.exp @@ -49,7 +49,7 @@ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/isa/*.\[cSi\]]] \ ${default_c_flags} "" gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/others/*.\[cSi\]]] \ - "" "-mcpu=v6.00.a" + "" "-mcpu=v10.0" # All done.