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[209.132.180.131]) by mx.google.com with ESMTPS id k7si4945221pak.202.2016.11.10.09.12.31 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 10 Nov 2016 09:12:31 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-440988-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-440988-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-440988-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; q=dns; s=default; b=K/tzwrzN3qBbK+jdETCz/IFIhAw104s/vY4mtUS25h9ajx+1Nm KHmrQM/LLf1GXt7nyYNliyxPIuiaUs0HC/+FPEdqgq5mRFBe9uITUqKVDE7go0Mj InnlPp4q4+h9O2Fgy3RzpVUY4KIakhydgzahy1XawhJaa72Aq/9RAUIsQ= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; s= default; bh=Zcp8+daIjbAHgxuHIE/EiKodsMU=; b=gwNL8wCQh/+llYmes1pe T4EFCmTOKAZL2eU8cRttBYlrtuJ1UbAuYzMfXIUZEBFJjDYMPrTt4ESl6XWCAxvs 0QVQa/J1jMyvGxC14EaZWZ/Zmycx8T/HFQi3SvfsS/6oFuR+w8reSh3Dvsu8ENa6 L5d/oyjC0njTA+M8rgWcQ3E= Received: (qmail 66179 invoked by alias); 10 Nov 2016 17:12:00 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 66002 invoked by uid 89); 10 Nov 2016 17:11:53 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-4.0 required=5.0 tests=BAYES_00, KAM_ASCII_DIVIDERS, RP_MATCHES_RCVD, SPF_HELO_PASS autolearn=ham version=3.3.2 spammy=no_regs, voi, allocno, NO_REGS X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 10 Nov 2016 17:11:43 +0000 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 3C90F3F202 for ; Thu, 10 Nov 2016 17:11:42 +0000 (UTC) Received: from brix.home (ovpn-112-11.phx2.redhat.com [10.3.112.11]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id uAAHBeW8030720 for ; Thu, 10 Nov 2016 12:11:41 -0500 To: "gcc-patches@gcc.gnu.org" From: Vladimir N Makarov Subject: A RA patch necessary for new Intel insns generation Message-ID: <24bb0b52-2509-8937-82d7-bd9b7293acac@redhat.com> Date: Thu, 10 Nov 2016 12:11:39 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 MIME-Version: 1.0 X-IsSubscribed: yes Hi, the following patch is necessary for generation of new Intel insns requiring 4 aligned zmm regs. Committed as rev. 242043. Index: ChangeLog =================================================================== --- ChangeLog (revision 242040) +++ ChangeLog (working copy) @@ -1,3 +1,12 @@ +2016-11-10 Vladimir Makarov + + * target.def (additional_allocno_class_p): New. + * hooks.h (hook_bool_reg_class_t_false): New prototype. + * hooks.c (hook_bool_reg_class_t_false): New. + * ira.c (setup_allocno_and_important_classes): Use the new hook. + * doc/tm.texi.in (TARGET_ADDITIONAL_ALLOCNO_CLASS_P): Add it. + * doc/tm.texi: Update. + 2016-11-10 Jason Merrill * gengtype.c (new_structure): Append to structures list. Index: hooks.h =================================================================== --- hooks.h (revision 242040) +++ hooks.h (working copy) @@ -55,6 +55,7 @@ extern bool hook_bool_rtx_insn_true (rtx extern bool hook_bool_rtx_false (rtx); extern bool hook_bool_rtx_insn_int_false (rtx_insn *, int); extern bool hook_bool_uintp_uintp_false (unsigned int *, unsigned int *); +extern bool hook_bool_reg_class_t_false (reg_class_t regclass); extern bool hook_bool_rtx_mode_int_int_intp_bool_false (rtx, machine_mode, int, int, int *, bool); extern bool hook_bool_tree_tree_false (tree, tree); Index: hooks.c =================================================================== --- hooks.c (revision 242040) +++ hooks.c (working copy) @@ -466,3 +466,11 @@ hook_bool_uint_uintp_false (unsigned int { return false; } + +/* Generic hook that takes a register class and returns false. */ +bool +hook_bool_reg_class_t_false (reg_class_t regclass ATTRIBUTE_UNUSED) +{ + return false; +} + Index: target.def =================================================================== --- target.def (revision 242040) +++ target.def (working copy) @@ -5029,6 +5029,18 @@ DEFHOOK reg_class_t, (reg_class_t, machine_mode), NULL) +/* Determine an additional allocno class. */ +DEFHOOK +(additional_allocno_class_p, + "This hook should return @code{true} if given class of registers should\ + be an allocno class in any way. Usually RA uses only one register\ + class from all classes containing the same register set. In some\ + complicated cases, you need to have two or more such classes as\ + allocno ones for RA correct work. Not defining this hook is\ + equivalent to returning @code{false} for all inputs.", + bool, (reg_class_t), + hook_bool_reg_class_t_false) + DEFHOOK (cstore_mode, "This hook defines the machine mode to use for the boolean result of\ Index: ira.c =================================================================== --- ira.c (revision 242040) +++ ira.c (working copy) @@ -1012,7 +1012,7 @@ setup_allocno_and_important_classes (voi temp_hard_regset2)) break; } - if (j >= n) + if (j >= n || targetm.additional_allocno_class_p (i)) classes[n++] = (enum reg_class) i; else if (i == GENERAL_REGS) /* Prefer general regs. For i386 example, it means that Index: doc/tm.texi.in =================================================================== --- doc/tm.texi.in (revision 242040) +++ doc/tm.texi.in (working copy) @@ -2507,6 +2507,8 @@ value that the middle-end intended. @hook TARGET_SPILL_CLASS +@hook TARGET_ADDITIONAL_ALLOCNO_CLASS_P + @hook TARGET_CSTORE_MODE @hook TARGET_COMPUTE_PRESSURE_CLASSES Index: doc/tm.texi =================================================================== --- doc/tm.texi (revision 242040) +++ doc/tm.texi (working copy) @@ -2899,6 +2899,10 @@ addressing. This hook defines a class of registers which could be used for spilling pseudos of the given mode and class, or @code{NO_REGS} if only memory should be used. Not defining this hook is equivalent to returning @code{NO_REGS} for all inputs. @end deftypefn +@deftypefn {Target Hook} bool TARGET_ADDITIONAL_ALLOCNO_CLASS_P (reg_class_t) +This hook should return @code{true} if given class of registers should be an allocno class in any way. Usually RA uses only one register class from all classes containing the same register set. In some complicated cases, you need to have two or more such classes as allocno ones for RA correct work. Not defining this hook is equivalent to returning @code{false} for all inputs. +@end deftypefn + @deftypefn {Target Hook} machine_mode TARGET_CSTORE_MODE (enum insn_code @var{icode}) This hook defines the machine mode to use for the boolean result of conditional store patterns. The ICODE argument is the instruction code for the cstore being performed. Not definiting this hook is the same as accepting the mode encoded into operand 0 of the cstore expander patterns. @end deftypefn