From patchwork Wed Jan 17 14:55:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Richard Earnshaw \(lists\)" X-Patchwork-Id: 124808 Delivered-To: patch@linaro.org Received: by 10.46.62.1 with SMTP id l1csp70822lja; Wed, 17 Jan 2018 06:56:34 -0800 (PST) X-Google-Smtp-Source: ACJfBouTCD52BOQQLyY0grRGR9xYmXCxtlSTgSHCHxJowfOh10+kyV9a4revwCU3s/YaEwg3SZJa X-Received: by 10.84.232.202 with SMTP id x10mr5689842plm.367.1516200994438; Wed, 17 Jan 2018 06:56:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516200994; cv=none; d=google.com; s=arc-20160816; b=tSfYvdM2ERhH8YnQqaqas4J+WT2bJvgemhKkDf1s/cG6DlQVJx6lDDQiKwZr7Dfjvs xtC7DgHvQdHP3GrpNeH/ITIQKZBR8s5xVl09ciswTihiZbCPdM/1CfiIhcUqy2pD/HGH WIe2h72cQ4CLHam/aKzdCWVJzC+QFj5awhfqk12MWGmskVJ5wnI2P4GIrX5hitHo+2qA jblokV+yultLI7hgvzLk2LvglzcSLkwzekbV1QOIftDaSaTiJP6xS9m+RQdd5v0rq59p WH5Nr+ar4V0/o2HrlkPoip4s1Z7b7Ed8zHq/l8HNukWiseI5FKthwLssJDGZd2BlbUVN Se5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:references:in-reply-to:references:in-reply-to :message-id:date:subject:cc:to:from:delivered-to:sender:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence :mailing-list:dkim-signature:domainkey-signature :arc-authentication-results; bh=568cOZwEGtggUnppCLEjbi15SvYToOhv7iLaG/MK0to=; b=Bm/K4SvyPoRSvbNr3scmhDHGX/50lopERonNQkpab3v0+awTp1UVon1jCzyqlCKtmt 1ExzYL5dRva7jSyKLopfzdmIrAjKLN3XfNRTCx5/oAbrRgr0gDNYQaeRt9k26NJLAZu7 1dzK2QCrV2UZPWHTZXi0hE/E6I397k1EaLsQJtNzJJ82Y0u1pPqsTR6VRVFIA4Bg/TWV 5iKF2FTnLAT4ctVHsUYdlJc4MW+F5xZr8uPOrL/FdAL4cQoOsbPa9fFdYFIodJt4hcJe jC/cRh0ELMU/odRvZKivUEbXon3mZOGzYPgVPy22aF5ratAaVXvUbRNm8DJWYs+x4lpK TmZg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=lUH4RT5I; spf=pass (google.com: domain of gcc-patches-return-471477-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-471477-patch=linaro.org@gcc.gnu.org Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id e4si4518389pfb.84.2018.01.17.06.56.34 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 17 Jan 2018 06:56:34 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-471477-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=lUH4RT5I; spf=pass (google.com: domain of gcc-patches-return-471477-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-471477-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references:mime-version:content-type; q=dns; s= default; b=PrrQq20qupL1NFcgscaNjMqjnyCt6Enl2t2qrdmc6pxoHf3TMaP8v SVmcdb4WuQz8DPPz7bwKSVDuOjpY9GtqCD06kzatRQIRInloaiIPKrx6uBxpwA3k 9wePBJ9bSiwQ868T2TUh9TfOLJXge/jQ0qxxOjtR8tQ56ZRh/fG0mc= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references:mime-version:content-type; s=default; bh=28EjefTxx1zs6/kjFDaaQFwW2Zc=; b=lUH4RT5IUggTzPkavdBFZCbIIBLd ccDVLQZY95TKkjO0o1VJMFpEiF5ppdblWbXEvkh2DpzwEcNEj2eLSXmR4sIHWOF/ ueJPGztEllXqpMDSD0vZp3FoLt8G1iSBiWKMFrAok2BIS4ty7Z3Y/3Hr+c9lj44e 8UoQ19FYHawufsY= Received: (qmail 84721 invoked by alias); 17 Jan 2018 14:56:12 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 84627 invoked by uid 89); 17 Jan 2018 14:56:12 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS, T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=numbered X-HELO: foss.arm.com Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 17 Jan 2018 14:56:10 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D0D6A15AD; Wed, 17 Jan 2018 06:56:08 -0800 (PST) Received: from e105689-lin.cambridge.arm.com (e105689-lin.cambridge.arm.com [10.2.207.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 14D9D3F557; Wed, 17 Jan 2018 06:56:07 -0800 (PST) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [PATCH 2/3] [aarch64] Implement support for __builtin_speculation_safe_load Date: Wed, 17 Jan 2018 14:55:35 +0000 Message-Id: <38bc3149ec21722caba728bae9dab5381514a4e4.1516199099.git.Richard.Earnshaw@arm.com> In-Reply-To: References: In-Reply-To: References: MIME-Version: 1.0 This patch implements support for __builtin_speculation_safe_load on AArch64. On this architecture we inhibit speclation by emitting a combination of CSEL and a hint instruction that ensures the CSEL is full resolved when the operands to the CSEL may involve a speculative load. * config/aarch64/aarch64.c (aarch64_print_operand): Handle zero passed to 'H' operand qualifier. (aarch64_speculation_safe_load): New function. (TARGET_SPECULATION_SAFE_LOAD): Redefine. * config/aarch64/aarch64.md (UNSPECV_NOSPECULATE): New unspec_volatile code. (nospeculate, nospeculateti): New patterns. --- gcc/config/aarch64/aarch64.c | 81 +++++++++++++++++++++++++++++++++++++++++++ gcc/config/aarch64/aarch64.md | 28 +++++++++++++++ 2 files changed, 109 insertions(+) diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 93e9d9f9..6591d19 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -5315,6 +5315,14 @@ aarch64_print_operand (FILE *f, rtx x, int code) break; case 'H': + /* Print the higher numbered register of a pair (TImode) of regs. */ + if (x == const0_rtx + || (CONST_DOUBLE_P (x) && aarch64_float_const_zero_rtx_p (x))) + { + asm_fprintf (f, "xzr"); + break; + } + if (!REG_P (x) || !GP_REGNUM_P (REGNO (x) + 1)) { output_operand_lossage ("invalid operand for '%%%c'", code); @@ -15115,6 +15123,76 @@ aarch64_sched_can_speculate_insn (rtx_insn *insn) } } +static rtx +aarch64_speculation_safe_load (machine_mode mode, rtx result, rtx mem, + rtx lower_bound, rtx upper_bound, rtx cmpptr, + bool warn ATTRIBUTE_UNUSED) +{ + rtx cond, comparison; + rtx target = gen_reg_rtx (mode); + rtx tgt2 = result; + + if (!register_operand (cmpptr, ptr_mode)) + cmpptr = force_reg (ptr_mode, cmpptr); + + if (!register_operand (tgt2, mode)) + tgt2 = gen_reg_rtx (mode); + + if (lower_bound == const0_rtx) + { + if (!register_operand (upper_bound, ptr_mode)) + upper_bound = force_reg (ptr_mode, upper_bound); + + cond = aarch64_gen_compare_reg (GEU, cmpptr, upper_bound); + comparison = gen_rtx_GEU (VOIDmode, cond, const0_rtx); + } + else + { + if (!register_operand (lower_bound, ptr_mode)) + lower_bound = force_reg (ptr_mode, lower_bound); + + if (!register_operand (upper_bound, ptr_mode)) + upper_bound = force_reg (ptr_mode, upper_bound); + + rtx cond1 = aarch64_gen_compare_reg (GEU, cmpptr, lower_bound); + rtx comparison1 = gen_rtx_GEU (ptr_mode, cond1, const0_rtx); + rtx failcond = GEN_INT (aarch64_get_condition_code (comparison1)^1); + cond = gen_rtx_REG (CCmode, CC_REGNUM); + if (ptr_mode == SImode) + emit_insn (gen_ccmpsi (cond1, cond, cmpptr, upper_bound, comparison1, + failcond)); + else + emit_insn (gen_ccmpdi (cond1, cond, cmpptr, upper_bound, comparison1, + failcond)); + comparison = gen_rtx_GEU (VOIDmode, cond, const0_rtx); + } + + rtx_code_label *label = gen_label_rtx (); + emit_jump_insn (gen_condjump (comparison, cond, label)); + emit_move_insn (target, mem); + emit_label (label); + + insn_code icode; + + switch (mode) + { + case E_QImode: icode = CODE_FOR_nospeculateqi; break; + case E_HImode: icode = CODE_FOR_nospeculatehi; break; + case E_SImode: icode = CODE_FOR_nospeculatesi; break; + case E_DImode: icode = CODE_FOR_nospeculatedi; break; + case E_TImode: icode = CODE_FOR_nospeculateti; break; + default: + gcc_unreachable (); + } + + emit_insn (GEN_FCN (icode) (tgt2, comparison, cond, target, const0_rtx)); + + if (tgt2 != result) + emit_move_insn (result, tgt2); + + return result; +} + /* Target-specific selftests. */ #if CHECKING_P @@ -15554,6 +15632,9 @@ aarch64_libgcc_floating_mode_supported_p #undef TARGET_CONSTANT_ALIGNMENT #define TARGET_CONSTANT_ALIGNMENT aarch64_constant_alignment +#undef TARGET_SPECULATION_SAFE_LOAD +#define TARGET_SPECULATION_SAFE_LOAD aarch64_speculation_safe_load + #if CHECKING_P #undef TARGET_RUN_TARGET_SELFTESTS #define TARGET_RUN_TARGET_SELFTESTS selftest::aarch64_run_selftests diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index f1e2a07..1a1f398 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -153,6 +153,7 @@ UNSPECV_SET_FPSR ; Represent assign of FPSR content. UNSPECV_BLOCKAGE ; Represent a blockage UNSPECV_PROBE_STACK_RANGE ; Represent stack range probing. + UNSPECV_NOSPECULATE ; Inhibit speculation ] ) @@ -5797,6 +5798,33 @@ DONE; }) +(define_insn "nospeculate" + [(set (match_operand:ALLI 0 "register_operand" "=r") + (unspec_volatile:ALLI + [(match_operator 1 "aarch64_comparison_operator" + [(match_operand 2 "cc_register" "") (const_int 0)]) + (match_operand:ALLI 3 "register_operand" "r") + (match_operand:ALLI 4 "aarch64_reg_or_zero" "rZ")] + UNSPECV_NOSPECULATE))] + "" + "csel\\t%0, %3, %4, %M1\;hint\t#0x14\t// CSDB" + [(set_attr "type" "csel") + (set_attr "length" "8")] +) + +(define_insn "nospeculateti" + [(set (match_operand:TI 0 "register_operand" "=r") + (unspec_volatile:TI + [(match_operator 1 "aarch64_comparison_operator" + [(match_operand 2 "cc_register" "") (const_int 0)]) + (match_operand:TI 3 "register_operand" "r") + (match_operand:TI 4 "aarch64_reg_or_zero" "rZ")] + UNSPECV_NOSPECULATE))] + "" + "csel\\t%x0, %x3, %x4, %M1\;csel\\t%H0, %H3, %H4, %M1\;hint\t#0x14\t// CSDB" + [(set_attr "type" "csel") + (set_attr "length" "12")] +) ;; AdvSIMD Stuff (include "aarch64-simd.md")