From patchwork Fri May 27 16:36:23 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Stubbs X-Patchwork-Id: 1657 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:53:56 -0000 Delivered-To: patches@linaro.org Received: by 10.52.181.230 with SMTP id dz6cs95129vdc; Fri, 27 May 2011 09:36:29 -0700 (PDT) Received: by 10.42.64.200 with SMTP id h8mr1786086ici.276.1306514189167; Fri, 27 May 2011 09:36:29 -0700 (PDT) Received: from mail.codesourcery.com (mail.codesourcery.com [38.113.113.100]) by mx.google.com with ESMTPS id f8si3521803icy.145.2011.05.27.09.36.28 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 27 May 2011 09:36:29 -0700 (PDT) Received-SPF: pass (google.com: domain of ams@codesourcery.com designates 38.113.113.100 as permitted sender) client-ip=38.113.113.100; Authentication-Results: mx.google.com; spf=pass (google.com: domain of ams@codesourcery.com designates 38.113.113.100 as permitted sender) smtp.mail=ams@codesourcery.com Received: (qmail 20505 invoked from network); 27 May 2011 16:36:27 -0000 Received: from unknown (HELO ?192.168.0.100?) (ams@127.0.0.2) by mail.codesourcery.com with ESMTPA; 27 May 2011 16:36:27 -0000 Message-ID: <4DDFD307.6010808@codesourcery.com> Date: Fri, 27 May 2011 17:36:23 +0100 From: Andrew Stubbs Organization: CodeSourcery User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.17) Gecko/20110424 Lightning/1.0b2 Thunderbird/3.1.10 MIME-Version: 1.0 To: gcc-patches@gcc.gnu.org, patches@linaro.org Subject: [PATCH][ARM] add support for some missing 16-bit multiplication insns Hi all, This patch adds support for the ARM SMLALTB, SMLALTT, SMLATB, and SMLATT instructions. These instructions do HImode -> DI/SImode widening multiply-and-accumulate with one or both operands taken from the top 16 bits of the source register. Note that this patch won't do much until my other patch for canonical mult patterns is applied. OK? Andrew 2011-05-27 Andrew Stubbs gcc/ * config/arm/arm.md (*maddhidi4tb, *maddhidi4tt): New define_insns. (*maddhisi4tb, *maddhisi4tt): New define_insns. gcc/testsuite/ * gcc.target/arm/smlatb-1.c: New file. * gcc.target/arm/smlatt-1.c: New file. * gcc.target/arm/smlaltb-1.c: New file. * gcc.target/arm/smlaltt-1.c: New file. --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -1815,6 +1815,36 @@ (set_attr "predicable" "yes")] ) +;; Note: there is no maddhisi4ibt because this one is canonical form +(define_insn "*maddhisi4tb" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (plus:SI (mult:SI (ashiftrt:SI + (match_operand:SI 1 "s_register_operand" "r") + (const_int 16)) + (sign_extend:SI + (match_operand:HI 2 "s_register_operand" "r"))) + (match_operand:SI 3 "s_register_operand" "r")))] + "TARGET_DSP_MULTIPLY" + "smlatb%?\\t%0, %1, %2, %3" + [(set_attr "insn" "smlaxy") + (set_attr "predicable" "yes")] +) + +(define_insn "*maddhisi4tt" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (plus:SI (mult:SI (ashiftrt:SI + (match_operand:SI 1 "s_register_operand" "r") + (const_int 16)) + (ashiftrt:SI + (match_operand:SI 2 "s_register_operand" "r") + (const_int 16))) + (match_operand:SI 3 "s_register_operand" "r")))] + "TARGET_DSP_MULTIPLY" + "smlatt%?\\t%0, %1, %2, %3" + [(set_attr "insn" "smlaxy") + (set_attr "predicable" "yes")] +) + (define_insn "*maddhidi4" [(set (match_operand:DI 0 "s_register_operand" "=r") (plus:DI @@ -1828,6 +1858,39 @@ [(set_attr "insn" "smlalxy") (set_attr "predicable" "yes")]) +;; Note: there is no maddhidi4ibt because this one is canonical form +(define_insn "*maddhidi4tb" + [(set (match_operand:DI 0 "s_register_operand" "=r") + (plus:DI + (mult:DI (sign_extend:DI + (ashiftrt:SI + (match_operand:SI 1 "s_register_operand" "r") + (const_int 16))) + (sign_extend:DI + (match_operand:HI 2 "s_register_operand" "r"))) + (match_operand:DI 3 "s_register_operand" "0")))] + "TARGET_DSP_MULTIPLY" + "smlaltb%?\\t%Q0, %R0, %1, %2" + [(set_attr "insn" "smlalxy") + (set_attr "predicable" "yes")]) + +(define_insn "*maddhidi4tt" + [(set (match_operand:DI 0 "s_register_operand" "=r") + (plus:DI + (mult:DI (sign_extend:DI + (ashiftrt:SI + (match_operand:SI 1 "s_register_operand" "r") + (const_int 16))) + (sign_extend:DI + (ashiftrt:SI + (match_operand:SI 2 "s_register_operand" "r") + (const_int 16)))) + (match_operand:DI 3 "s_register_operand" "0")))] + "TARGET_DSP_MULTIPLY" + "smlaltt%?\\t%Q0, %R0, %1, %2" + [(set_attr "insn" "smlalxy") + (set_attr "predicable" "yes")]) + (define_expand "mulsf3" [(set (match_operand:SF 0 "s_register_operand" "") (mult:SF (match_operand:SF 1 "s_register_operand" "") --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/smlaltb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv7-a" } */ + +long long int +foo (long long x, int in) +{ + short a = in & 0xffff; + short b = (in & 0xffff0000) >> 16; + + return x + b * a; +} + +/* { dg-final { scan-assembler "smlaltb" } } */ --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/smlaltt-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv7-a" } */ + +long long int +foo (long long x, int in1, int in2) +{ + short a = (in1 & 0xffff0000) >> 16; + short b = (in2 & 0xffff0000) >> 16; + + return x + b * a; +} + +/* { dg-final { scan-assembler "smlaltt" } } */ --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/smlatb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv7-a" } */ + +int +foo (int x, int in) +{ + short a = in & 0xffff; + short b = (in & 0xffff0000) >> 16; + + return x + b * a; +} + +/* { dg-final { scan-assembler "smlatb" } } */ --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/smlatt-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv7-a" } */ + +int +foo (int x, int in1, int in2) +{ + short a = (in1 & 0xffff0000) >> 16; + short b = (in2 & 0xffff0000) >> 16; + + return x + b * a; +} + +/* { dg-final { scan-assembler "smlatt" } } */