From patchwork Fri Jun 3 08:32:43 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramana Radhakrishnan X-Patchwork-Id: 1732 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:55:03 -0000 Delivered-To: patches@linaro.org Received: by 10.52.181.10 with SMTP id ds10cs3792vdc; Fri, 3 Jun 2011 01:32:45 -0700 (PDT) Received: by 10.227.32.84 with SMTP id b20mr1611099wbd.105.1307089964345; Fri, 03 Jun 2011 01:32:44 -0700 (PDT) Received: from mail-ww0-f42.google.com (mail-ww0-f42.google.com [74.125.82.42]) by mx.google.com with ESMTPS id o2si2713769wbh.44.2011.06.03.01.32.43 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 03 Jun 2011 01:32:44 -0700 (PDT) Received-SPF: neutral (google.com: 74.125.82.42 is neither permitted nor denied by best guess record for domain of ramana.radhakrishnan@linaro.org) client-ip=74.125.82.42; Authentication-Results: mx.google.com; spf=neutral (google.com: 74.125.82.42 is neither permitted nor denied by best guess record for domain of ramana.radhakrishnan@linaro.org) smtp.mail=ramana.radhakrishnan@linaro.org Received: by wwk4 with SMTP id 4so4889801wwk.1 for ; Fri, 03 Jun 2011 01:32:43 -0700 (PDT) Received: by 10.227.24.8 with SMTP id t8mr1670233wbb.0.1307089963758; Fri, 03 Jun 2011 01:32:43 -0700 (PDT) Received: from [192.168.32.37] (fw-lnat.cambridge.arm.com [217.140.96.63]) by mx.google.com with ESMTPS id ge4sm874737wbb.47.2011.06.03.01.32.42 (version=SSLv3 cipher=OTHER); Fri, 03 Jun 2011 01:32:42 -0700 (PDT) Message-ID: <4DE89C2B.8050006@linaro.org> Date: Fri, 03 Jun 2011 09:32:43 +0100 From: Ramana Radhakrishnan User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.17) Gecko/20110424 Lightning/1.0b2 Thunderbird/3.1.10 MIME-Version: 1.0 To: gcc-patches@gcc.gnu.org CC: Patch Tracking , Michael Hope Subject: Re: [Patch ARM] Unbreak bootstrap for --with-fpu=neon. References: In-Reply-To: On 01/06/11 18:27, Ramana Radhakrishnan wrote: > 2011-05-31 Ramana Radhakrishnan > > * config/arm/neon.md (orndi3_neon): Actually split it. This is what I committed in the end after a round of testing. Ramana Index: gcc/config/arm/neon.md =================================================================== --- gcc/config/arm/neon.md (revision 174596) +++ gcc/config/arm/neon.md (working copy) @@ -801,17 +801,44 @@ [(set_attr "neon_type" "neon_int_1")] ) -(define_insn "orndi3_neon" - [(set (match_operand:DI 0 "s_register_operand" "=w,?=&r,?&r") - (ior:DI (not:DI (match_operand:DI 2 "s_register_operand" "w,0,r")) - (match_operand:DI 1 "s_register_operand" "w,r,0")))] +;; TODO: investigate whether we should disable +;; this and bicdi3_neon for the A8 in line with the other +;; changes above. +(define_insn_and_split "orndi3_neon" + [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r,?&r") + (ior:DI (not:DI (match_operand:DI 2 "s_register_operand" "w,0,0,r")) + (match_operand:DI 1 "s_register_operand" "w,r,r,0")))] "TARGET_NEON" "@ vorn\t%P0, %P1, %P2 # + # #" - [(set_attr "neon_type" "neon_int_1,*,*") - (set_attr "length" "*,8,8")] + "reload_completed && + (TARGET_NEON && !(IS_VFP_REGNUM (REGNO (operands[0]))))" + [(set (match_dup 0) (ior:SI (not:SI (match_dup 2)) (match_dup 1))) + (set (match_dup 3) (ior:SI (not:SI (match_dup 4)) (match_dup 5)))] + " + { + if (TARGET_THUMB2) + { + operands[3] = gen_highpart (SImode, operands[0]); + operands[0] = gen_lowpart (SImode, operands[0]); + operands[4] = gen_highpart (SImode, operands[2]); + operands[2] = gen_lowpart (SImode, operands[2]); + operands[5] = gen_highpart (SImode, operands[1]); + operands[1] = gen_lowpart (SImode, operands[1]); + } + else + { + emit_insn (gen_one_cmpldi2 (operands[0], operands[2])); + emit_insn (gen_iordi3 (operands[0], operands[1], operands[0])); + DONE; + } + }" + [(set_attr "neon_type" "neon_int_1,*,*,*") + (set_attr "length" "*,16,8,8") + (set_attr "arch" "any,a,t2,t2")] ) (define_insn "bic3_neon"